Document Renesas RZ/G2UL pinctrl bindings. RZ/G2UL GPIO block is
almost identical to RZ/G2L and has lesser pins compared to RZ/G2L.
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
---
.../bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
index 08ea34f39574..71057e570e49 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
@@ -11,8 +11,8 @@ maintainers:
- Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
description:
- The Renesas SoCs of the RZ/{G2L,V2L} series feature a combined Pin and GPIO
- controller.
+ The Renesas SoCs of the RZ/{G2L,V2L} alike series feature a combined Pin and
+ GPIO controller.
Pin multiplexing and GPIO configuration is performed on a per-pin basis.
Each port features up to 8 pins, each of them configurable for GPIO function
(port mode) or in alternate function mode.
@@ -21,6 +21,10 @@ description:
properties:
compatible:
oneOf:
+ - items:
+ - enum:
+ - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2}
+
- items:
- enum:
- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
--
2.17.1
