On 11/03/2022 11:42, Krzysztof Kozlowski wrote: > On 11/03/2022 10:45, Vincent Whitchurch wrote: >> Add support for the UART block on the ARTPEC-8 SoC. This is closely >> related to the variants used on the Exynos chips. The register layout >> is identical to Exynos850 et al but the fifo size is different (64 bytes >> in each direction for all instances). >> >> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxxxxx> >> Signed-off-by: Vincent Whitchurch <vincent.whitchurch@xxxxxxxx> >> --- >> >> Notes: >> v2: >> - Added Krzysztof's Reviewed-by. >> - Expanded commit message >> - Fixed fifo size >> - Rebased on top of Krzysztof's "minor fixes/cleanups" series. This needed a >> couple of fixes for build errors. >> >> (I'm always unsure if Reviewed-by should be carried over or not if the fixes >> are minor. I apologize in advance if carring it over was the wrong thing to do >> in this case.) > > For minor fixes, usually we carry Rb tag over. It's fine. > Hi Greg, Just one note for you - this depends now on my v3 patchset here: https://lore.kernel.org/all/20220308080919.152715-1-krzysztof.kozlowski@xxxxxxxxxxxxx/ Best regards, Krzysztof
