On Mon, 28 Feb 2022 16:15:45 +0100, Christophe Leroy wrote: > Some components require a few clock cycles with chipselect off before > or/and after the data transfer done with CS on. > > Typically IDT 801034 QUAD PCM CODEC datasheet states "Note *: CCLK > should have one cycle before CS goes low, and two cycles after > CS goes high". > > The cycles "before" are implicitely provided by all previous activity > on the SPI bus. But the cycles "after" must be provided in order to > achieve the SPI transfer. > > In order to use that kind of component, implement a new option for > SPI slaves in order to implement trailing clock of a given number of > bits with ChipSelect off at the end of the transfer. > > Signed-off-by: Christophe Leroy <christophe.leroy@xxxxxxxxxx> > --- > .../devicetree/bindings/spi/spi-peripheral-props.yaml | 5 +++++ > drivers/spi/spi.c | 7 +++++-- > include/linux/spi/spi.h | 1 + > 3 files changed, 11 insertions(+), 2 deletions(-) > Acked-by: Rob Herring <robh@xxxxxxxxxx>
