This series implements Sstc extension support which was ratified recently. Before the Sstc extension, an SBI call is necessary to generate timer interrupts as only M-mode have access to the timecompare registers. Thus, there is significant latency to generate timer interrupts at kernel. For virtualized enviornments, its even worse as the KVM handles the SBI call and uses a software timer to emulate the timecomapre register. Sstc extension solves both these problems by defining a stimecmp/vstimecmp at supervisor (host/guest) level. It allows kernel to program a timer and recieve interrupt without supervisor execution enviornment (M-mode/HS mode) intervention. To maintain backward compatibility, KVM directly updates the vstimecmp if older kernel without sstc support is running in guest. Similary, the M-mode firmware(OpenSBI) uses stimecmp for older kernel without sstc support. The PATCH 1 & 2 enables the basic infrastructure around Sstc extension while PATCH 3 lets kernel use the Sstc extension if it is available in hardware. PATCH 4 & 5 adds the infrastructure for KVM to use sstc while PATCH 6 actually uses the Sstc extension if available. This series has been tested on Qemu(RV32 & RV64) with additional patches in OpenSBI[2] and Qemu[3]. This series can also be found at [4]. Changes from v1->v2: 1. Separate the static key from kvm usage 2. Makde the sstc specific static key local to the driver/clocksource 3. Moved the vstimecmp update code to the vcpu_timer 4. Used function pointers instead of static key to invoke vstimecmp vs hrtimer at the run time. This will help in future for migration of vms from/to sstc enabled hardware to non-sstc enabled hardware. 5. Unified the vstimer & timer to 1 timer as only one of them will be used at runtime. [1] https://drive.google.com/file/d/1m84Re2yK8m_vbW7TspvevCDR82MOBaSX/view [2] https://github.com/atishp04/opensbi/tree/sstc_v1 [3] https://github.com/atishp04/qemu/tree/sstc_v1 [3] https://github.com/atishp04/linux/tree/sstc_v2 Atish Patra (7): RISC-V: Add SSTC extension CSR details RISC-V: Enable sstc extension parsing from DT RISC-V: Prefer sstc extension if available RISC-V: KVM: Remove 's' & 'u' as valid ISA extension RISC-V: KVM: Restrict the extensions that can be disabled RISC-V: KVM: Introduce ISA extension register RISC-V: KVM: Support sstc extension arch/riscv/include/asm/csr.h | 11 ++ arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/include/asm/kvm_host.h | 1 + arch/riscv/include/asm/kvm_vcpu_timer.h | 8 +- arch/riscv/include/uapi/asm/kvm.h | 21 ++++ arch/riscv/kernel/cpu.c | 1 + arch/riscv/kernel/cpufeature.c | 4 +- arch/riscv/kvm/main.c | 12 ++- arch/riscv/kvm/vcpu.c | 128 ++++++++++++++++++++-- arch/riscv/kvm/vcpu_timer.c | 138 +++++++++++++++++++++++- drivers/clocksource/timer-riscv.c | 21 +++- 11 files changed, 328 insertions(+), 18 deletions(-) -- 2.30.2
