Hello, Angelo, Many thanks for your review. On Thu, 2022-03-03 at 15:53 +0100, AngeloGioacchino Del Regno wrote: > Il 17/01/22 13:06, Irui Wang ha scritto: > > Adds encoder cores dt-bindings for mt8195 > > > > Signed-off-by: Irui Wang <irui.wang@xxxxxxxxxxxx> > > --- > > .../media/mediatek,vcodec-encoder-core.yaml | 214 > > ++++++++++++++++++ > > 1 file changed, 214 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/media/mediatek,vcodec-encoder- > > core.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder- > > core.yaml > > b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder- > > core.yaml > > new file mode 100644 > > index 000000000000..d1e7bfa50bce > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec- > > encoder-core.yaml > > @@ -0,0 +1,214 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > + > > +%YAML 1.2 > > +--- > > +$id: " > > http://devicetree.org/schemas/media/mediatek,vcodec-encoder-core.yaml# > > " > > +$schema: "http://devicetree.org/meta-schemas/core.yaml#"; > > + > > +title: Mediatek Video Encoder Accelerator With Multi Core > > + > > +maintainers: > > + - Irui Wang <irui.wang@xxxxxxxxxxxx> > > + > > +description: | > > + Mediatek Video Encode is the video encode hardware present in > > Mediatek > > + SoCs which supports high resolution encoding functionalities. > > Required > > + parent and child device node. > > + > > +properties: > > + compatible: > > + const: mediatek,mt8195-vcodec-enc > > + > > + mediatek,scp: > > + $ref: /schemas/types.yaml#/definitions/phandle > > + maxItems: 1 > > + description: | > > + The node of system control processor (SCP), using > > + the remoteproc & rpmsg framework. > > + > > + iommus: > > + minItems: 1 > > + maxItems: 32 > > + description: | > > + List of the hardware port in respective IOMMU block for > > current Socs. > > + Refer to bindings/iommu/mediatek,iommu.yaml. > > + > > + dma-ranges: > > + maxItems: 1 > > + description: | > > + Describes the physical address space of IOMMU maps to > > memory. > > + > > + "#address-cells": > > + const: 1 > > + > > + "#size-cells": > > + const: 1 > > + > > + ranges: true > > + > > +# Required child node: > > +patternProperties: > > + "venc_core0@1a020000": > > This should be a pattern, venc-coreN where N is a number between 0 > and 9, > and any iostart should be allowed, not just 1a020000; doing it that > way > allows you to do a spec for all the core subnodes in one. I will fix it. > > > > + type: object > > + > > + properties: > > + compatible: > > + const: mediatek,mtk-venc-core0 > > + > > ..snip.. > > > + > > +required: > > + - compatible > > + - mediatek,scp > > + - iommus > > + - dma-ranges > > + - ranges > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + #include <dt-bindings/memory/mt8195-memory-port.h> > > + #include <dt-bindings/interrupt-controller/irq.h> > > + #include <dt-bindings/clock/mt8195-clk.h> > > + #include <dt-bindings/power/mt8195-power.h> > > + > > + venc { > > + compatible = "mediatek,mt8195-vcodec-enc"; > > + mediatek,scp = <&scp>; > > + iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>; > > + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges; > > What about doing instead... > > #address-cells = <2>; > #size-cells = <2>; > (or fix your dma-ranges property) cells=2 may cause some unexpected errors, I will check it again. > > and... > > ranges = <0 0 0 0x1a020000 0 0x1020000>; > venc-core0@0 { > compatible = "mediatek,mtk-venc-hw"; > reg = <0 0 0 0x10000>; > mediatek,hw-leader; > ..... other properties ..... > }; > > venc-core1@1000000 { > compatible = "mediatek,mtk-venc-hw"; > reg = <0 0x1000000 0 0x10000>; > ..... other properties ..... > } > > Regards, > Angelo I will rewrite the examples. Thanks Best Regards > > > + > > + venc_core0@1a020000 { > > + compatible = "mediatek,mtk-venc-core0"; > > + reg = <0x1a020000 0x10000>; > > + iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>, > > + <&iommu_vdo M4U_PORT_L19_VENC_REC>, > > + <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>, > > + <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>, > > + <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>, > > + <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>, > > + <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>, > > + <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, > > + <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; > > + interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>; > > + clocks = <&vencsys CLK_VENC_VENC>; > > + clock-names = "MT_CG_VENC0"; > > + assigned-clocks = <&topckgen CLK_TOP_VENC>; > > + assigned-clock-parents = <&topckgen > > CLK_TOP_UNIVPLL_D4>; > > + power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; > > + }; > > + > > + venc_core1@1b020000 { > > + compatible = "mediatek,mtk-venc-core1"; > > + reg = <0x1b020000 0x10000>; > > + iommus = <&iommu_vpp M4U_PORT_L20_VENC_RCPU>, > > + <&iommu_vpp M4U_PORT_L20_VENC_REC>, > > + <&iommu_vpp M4U_PORT_L20_VENC_BSDMA>, > > + <&iommu_vpp M4U_PORT_L20_VENC_SV_COMV>, > > + <&iommu_vpp M4U_PORT_L20_VENC_RD_COMV>, > > + <&iommu_vpp M4U_PORT_L20_VENC_CUR_LUMA>, > > + <&iommu_vpp M4U_PORT_L20_VENC_CUR_CHROMA>, > > + <&iommu_vpp M4U_PORT_L20_VENC_REF_LUMA>, > > + <&iommu_vpp M4U_PORT_L20_VENC_REF_CHROMA>; > > + interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH 0>; > > + clocks = <&vencsys_core1 CLK_VENC_CORE1_VENC>; > > + clock-names = "MT_CG_VENC1"; > > + assigned-clocks = <&topckgen CLK_TOP_VENC>; > > + assigned-clock-parents = <&topckgen > > CLK_TOP_UNIVPLL_D4>; > > + power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; > > + }; > > + }; > >
