Am Montag, 28. Februar 2022, 21:17:29 CET schrieb Lucas Stach: > This adds the GPC and HSIO blk-ctrl nodes providing power control for > the high-speed (USB and PCIe) IOs. > > Signed-off-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx> > Reviewed-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx> > --- > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 71 +++++++++++++++++++++-- > 1 file changed, 65 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index > 6b840c05dd77..69e533add539 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > @@ -4,6 +4,7 @@ > */ > > #include <dt-bindings/clock/imx8mp-clock.h> > +#include <dt-bindings/power/imx8mp-power.h> > #include <dt-bindings/gpio/gpio.h> > #include <dt-bindings/input/input.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > @@ -475,6 +476,44 @@ src: reset-controller@30390000 { > interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; > #reset-cells = <1>; > }; > + > + gpc: gpc@303a0000 { > + compatible = "fsl,imx8mp-gpc"; > + reg = <0x303a0000 0x1000>; > + interrupt-parent = <&gic>; > + interrupt-controller; > + #interrupt-cells = <3>; > + > + pgc { > + #address-cells = <1>; > + #size-cells = <0>; > + > + pgc_pcie_phy: power- domain@1 { > + #power- domain-cells = <0>; > + reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>; > + }; > + > + pgc_usb1_phy: power- domain@2 { > + #power- domain-cells = <0>; > + reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>; > + }; > + > + pgc_usb2_phy: power- domain@3 { > + #power- domain-cells = <0>; > + reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>; > + }; > + > + pgc_hsiomix: power- domains@17 { > + #power- domain-cells = <0>; > + reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>; > + clocks = <&clk IMX8MP_CLK_HSIO_AXI>, > + <&clk IMX8MP_CLK_HSIO_ROOT>; > + assigned- clocks = <&clk IMX8MP_CLK_HSIO_AXI>; > + assigned- clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; > + assigned- clock-rates = <500000000>; > + }; > + }; > + }; > }; > > aips2: bus@30400000 { > @@ -892,6 +931,28 @@ eqos: ethernet@30bf0000 { > }; > }; > > + aips4 { > + compatible = "fsl,aips-bus", "simple-bus"; > + reg = <0x32c00000 0x400000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + hsio_blk_ctrl: blk-ctrl@32f10000 { > + compatible = "fsl,imx8mp-hsio-blk- ctrl", "syscon"; > + reg = <0x32f10000 0x24>; > + clocks = <&clk IMX8MP_CLK_USB_ROOT>, > + <&clk IMX8MP_CLK_PCIE_ROOT>; > + clock-names = "usb", "pcie"; > + power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>, > + <&pgc_usb1_phy>, <&pgc_usb2_phy>, > + <&pgc_hsiomix>, <&pgc_pcie_phy>; > + power-domain-names = "bus", "usb", "usb-phy1", > + "usb- phy2", "pcie", "pcie-phy"; > + #power-domain-cells = <1>; > + }; > + }; > + > gic: interrupt-controller@38800000 { > compatible = "arm,gic-v3"; > reg = <0x38800000 0x10000>, > @@ -915,6 +976,7 @@ usb3_phy0: usb-phy@381f0040 { > clock-names = "phy"; > assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; > assigned-clock-parents = <&clk IMX8MP_CLK_24M>; > + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>; > #phy-cells = <0>; > status = "disabled"; > }; > @@ -926,6 +988,7 @@ usb3_0: usb@32f10100 { > <&clk IMX8MP_CLK_USB_ROOT>; > clock-names = "hsio", "suspend"; > interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; > + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; > #address-cells = <1>; > #size-cells = <1>; > dma-ranges = <0x40000000 0x40000000 0xc0000000>; > @@ -939,9 +1002,6 @@ usb_dwc3_0: usb@38100000 { > <&clk IMX8MP_CLK_USB_CORE_REF>, > <&clk IMX8MP_CLK_USB_ROOT>; > clock-names = "bus_early", "ref", "suspend"; > - assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; > - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; > - assigned-clock-rates = <500000000>; > interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; > phys = <&usb3_phy0>, <&usb3_phy0>; > phy-names = "usb2-phy", "usb3- phy"; > @@ -957,6 +1017,7 @@ usb3_phy1: usb-phy@382f0040 { > clock-names = "phy"; > assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; > assigned-clock-parents = <&clk IMX8MP_CLK_24M>; > + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>; > #phy-cells = <0>; > }; > > @@ -967,6 +1028,7 @@ usb3_1: usb@32f10108 { > <&clk IMX8MP_CLK_USB_ROOT>; > clock-names = "hsio", "suspend"; > interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; > + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; > #address-cells = <1>; > #size-cells = <1>; > dma-ranges = <0x40000000 0x40000000 0xc0000000>; > @@ -980,9 +1042,6 @@ usb_dwc3_1: usb@38200000 { > <&clk IMX8MP_CLK_USB_CORE_REF>, > <&clk IMX8MP_CLK_USB_ROOT>; > clock-names = "bus_early", "ref", "suspend"; > - assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; > - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; > - assigned-clock-rates = <500000000>; > interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; > phys = <&usb3_phy1>, <&usb3_phy1>; > phy-names = "usb2-phy", "usb3- phy"; Tested-by: Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx>