Add device tree nodes for PCIe0/PCIe1 controllers and corresponding
PHYs.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
index f0fcb1428449..5d6de95a3a84 100644
--- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
@@ -349,6 +349,27 @@ vreg_l7e_2p8: ldo7 {
};
};
+&pcie0 {
+ status = "okay";
+ max-link-speed = <2>;
+};
+
+&pcie0_phy {
+ status = "okay";
+ vdda-phy-supply = <&vreg_l5b_0p88>;
+ vdda-pll-supply = <&vreg_l6b_1p2>;
+};
+
+&pcie1 {
+ status = "okay";
+};
+
+&pcie1_phy {
+ status = "okay";
+ vdda-phy-supply = <&vreg_l2h_0p91>;
+ vdda-pll-supply = <&vreg_l6b_1p2>;
+};
+
&qupv3_id_0 {
status = "okay";
};
--
2.34.1
