On 28/02/2022 07:31, qinjian[覃健] wrote:
>>> +examples:
>>> + - |
>>> + clkc: clock-controller@9c000000 {
>>> + compatible = "sunplus,sp7021-clkc";
>>> + #clock-cells = <1>;
>>> + reg = <0x9c000000 0x280>;
>>> + clocks = <&extclk>, <&clkc PLL_SYS>;
>>
>> Except the warning pointed out by Rob's bot, it looks like you feed this
>> clock-controller with a clock from itself. Is there a point to express
>> it in DTS at all?
>
> Yes, pllsys is an internal clock, but it also as a parent clock for some other
> clocks in this clock-controller.
What is the point to express it in DTS? Usually such internal
parent-child relation is described in the driver.
And how does it even work? How can you get a clock from a device before
you registered that device?
Best regards,
Krzysztof
