On Sun, Feb 20, 2022 at 6:32 PM <michael.srba@xxxxxxxxx> wrote: > > From: Michael Srba <Michael.Srba@xxxxxxxxx> > > Adds bindings for the AHB bus which exposes the SCC block in the global > address space. This bus (and the SSC block itself) is present on certain > qcom SoCs. "SSC" or "SCC"? You have both and I suspect one is a typo. > > In typical configuration, this bus (as some of the clocks and registers > that we need to manipulate) is not accessible to the OS, and the > resources on this bus are indirectly accessed by communicating with a > hexagon CPU core residing in the SSC block. In this configuration, the > hypervisor is the one performing the bus initialization for the purposes > of bringing the haxagon CPU core out of reset. > > However, it is possible to change the configuration, in which case this > binding serves to allow the OS to initialize the bus. > > Signed-off-by: Michael Srba <Michael.Srba@xxxxxxxxx> > Reviewed-by: Rob Herring <robh@xxxxxxxxxx> > --- > CHANGES: > - v2: fix issues caught by by dt-schema > - v3: none > - v4: address the issues pointed out in the review > - v5: clarify type of additional properties; remove ssc_tlmm node for now > - v6: none > - v7: fix indentation, use imperative in commit message > - v8: none > --- > .../bindings/bus/qcom,ssc-block-bus.yaml | 143 ++++++++++++++++++ > 1 file changed, 143 insertions(+) > create mode 100644 Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml > > diff --git a/Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml b/Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml > new file mode 100644 > index 000000000000..4044af0afda8 > --- /dev/null > +++ b/Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml > @@ -0,0 +1,143 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/bus/qcom,ssc-block-bus.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: The AHB Bus Providing a Global View of the SSC Block on (some) qcom SoCs > + > +maintainers: > + - Michael Srba <Michael.Srba@xxxxxxxxx> > + > +description: | > + This binding describes the dependencies (clocks, resets, power domains) which > + need to be turned on in a sequence before communication over the AHB bus > + becomes possible. > + > + Additionally, the reg property is used to pass to the driver the location of > + two sadly undocumented registers which need to be poked as part of the sequence. Surely "SSC" is an acronym. Can you define it in the description? I suspect folks not familiar with 8998 will not know what it is.
