On 25/02/2022 23.39, Marc Zyngier wrote:
> On Thu, 24 Feb 2022 13:07:37 +0000,
>> if (!(pending & irq_bit) &&
>> - (atomic_read(per_cpu_ptr(&aic_vipi_enable, cpu)) & irq_bit))
>> - send |= AIC_IPI_SEND_CPU(cpu);
>> + (atomic_read(per_cpu_ptr(&aic_vipi_enable, cpu)) & irq_bit)) {
>> + if (static_branch_likely(&use_fast_ipi))
>> + aic_ipi_send_fast(cpu);
>
> OK, this is suffering from the same issue that GICv3 has, which is
> that memory barriers don't provide order against sysregs. You need a
> DSB for that, which is a pain. Something like this:
Doesn't the control flow here guarantee the ordering? atomic_read() must
complete before the sysreg is written since there is a control flow
dependency, and the prior atomic/barrier dance ensures that read is
ordered properly with everything that comes before it.
--
Hector Martin (marcan@xxxxxxxxx)
Public Key: https://mrcn.st/pub
