Hi Robin,
On 2/25/22 15:14, Robin Murphy wrote:
> On 2022-02-25 13:15, Michael Riesch wrote:
>> The power domain PD_PIPE was moved to the RK3568 specific dtsi but
>> is available on the RK3566 as well. Move it back to the shared dtsi.
>
> Note that a corresponding definition does already exist in rk3568.dtsi.
> That one *could* inherit the base definition and only override the
> "pm_qos" property, but looking back to the original patch series it
> seems like not doing that was a deliberate choice.
OK, my bad. I overlooked that both rk3566 and rk3568 have their
definition in their dtsi files, so there is no need for this patch.
Sorry for the confusion!
Best regards,
Michael
>
> Robin.
>
>> Signed-off-by: Michael Riesch <michael.riesch@xxxxxxxxxxxxxx>
>> ---
>> arch/arm64/boot/dts/rockchip/rk3568.dtsi | 16 ----------------
>> arch/arm64/boot/dts/rockchip/rk356x.dtsi | 14 ++++++++++++++
>> 2 files changed, 14 insertions(+), 16 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
>> b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
>> index 91a0b798b857..ecc0f3015915 100644
>> --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
>> +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
>> @@ -100,19 +100,3 @@ opp-1992000000 {
>> opp-microvolt = <1150000 1150000 1150000>;
>> };
>> };
>> -
>> -&power {
>> - power-domain@RK3568_PD_PIPE {
>> - reg = <RK3568_PD_PIPE>;
>> - clocks = <&cru PCLK_PIPE>;
>> - pm_qos = <&qos_pcie2x1>,
>> - <&qos_pcie3x1>,
>> - <&qos_pcie3x2>,
>> - <&qos_sata0>,
>> - <&qos_sata1>,
>> - <&qos_sata2>,
>> - <&qos_usb3_0>,
>> - <&qos_usb3_1>;
>> - #power-domain-cells = <0>;
>> - };
>> -};
>> diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
>> b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
>> index 8b9fae3d348a..742f5adcdf2b 100644
>> --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
>> +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
>> @@ -490,6 +490,20 @@ power-domain@RK3568_PD_RKVENC {
>> <&qos_rkvenc_wr_m0>;
>> #power-domain-cells = <0>;
>> };
>> +
>> + power-domain@RK3568_PD_PIPE {
>> + reg = <RK3568_PD_PIPE>;
>> + clocks = <&cru PCLK_PIPE>;
>> + pm_qos = <&qos_pcie2x1>,
>> + <&qos_pcie3x1>,
>> + <&qos_pcie3x2>,
>> + <&qos_sata0>,
>> + <&qos_sata1>,
>> + <&qos_sata2>,
>> + <&qos_usb3_0>,
>> + <&qos_usb3_1>;
>> + #power-domain-cells = <0>;
>> + };
>> };
>> };
>>
