On Tue, Feb 22, 2022 at 10:26:21AM +0530, Rohit Agarwal wrote: > Add information for Cortex A7 PLL clock in Qualcomm > platform SDX65. > > Signed-off-by: Rohit Agarwal <quic_rohiagar@xxxxxxxxxxx> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> Thanks, Mani > --- > Documentation/devicetree/bindings/clock/qcom,a7pll.yaml | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml > index 8666e99..0e96f69 100644 > --- a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml > +++ b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml > @@ -10,7 +10,7 @@ maintainers: > - Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> > > description: > - The A7 PLL on the Qualcomm platforms like SDX55 is used to provide high > + The A7 PLL on the Qualcomm platforms like SDX55, SDX65 is used to provide high > frequency clock to the CPU. > > properties: > -- > 2.7.4 >
