Hi,
(CC-ed DRM bridge maintainers and the dri-devel ML)
On Wed, Feb 2, 2022 at 1:47 AM Nícolas F. R. A. Prado
<nfraprado@xxxxxxxxxxxxx> wrote:
>
> mt8183-kukui-jacuzzi has an anx7625 bridge connected to the output of
> its DSI host. However, after commit fd0310b6fe7d ("drm/bridge: anx7625:
> add MIPI DPI input feature"), a bus-type property started being required
> in the endpoint node by the driver to indicate whether it is DSI or DPI.
>
> Add the missing bus-type property and set it to 5
> (V4L2_FWNODE_BUS_TYPE_PARALLEL) so that the driver has its input
> configured to DSI and the display pipeline can probe correctly.
Don't people find it odd that this is setting the bus-type to "parallel"
(5) for the device to use DSI? Instead of "MIPI CSI-2 D-PHY" (4) or even
"MIPI CSI-2 C-PHY" (1) which is specified in the binding? It's completely
backwards.
Would it be possible to fix the binding and driver at this point?
Thanks
ChenYu
> While at it, also set the data-lanes property that was also introduced
> in that same commit, so that we don't rely on the default value.
>
> Fixes: fd0310b6fe7d ("drm/bridge: anx7625: add MIPI DPI input feature")
> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@xxxxxxxxxxxxx>
>
> ---
> v1: https://lore.kernel.org/all/20220120224204.773117-1-nfraprado@xxxxxxxxxxxxx
>
> Changes in v2:
> - (thanks Rob) Use proper format when refering to commit in commit
> message as pointed out by checkpatch
>
> arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi
> index 8f7bf33f607d..e8f133dc96b9 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi
> @@ -171,6 +171,8 @@ port@0 {
>
> anx7625_in: endpoint {
> remote-endpoint = <&dsi_out>;
> + bus-type = <5>;
> + data-lanes = <0 1 2 3>;
> };
> };
>
> --
> 2.35.1
>
>
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