On Thu 17 Feb 17:56 CST 2022, Ansuel Smith wrote:
> Parent gcc_pxo_pll8_pll0 had the parent definition and parent map
> swapped. Fix this naming error.
>
> Signed-off-by: Ansuel Smith <ansuelsmth@xxxxxxxxx>
Reviewed-by: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx>
> ---
> drivers/clk/qcom/gcc-ipq806x.c | 20 ++++++++++----------
> 1 file changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
> index d6b7adb4be38..34cddf461dba 100644
> --- a/drivers/clk/qcom/gcc-ipq806x.c
> +++ b/drivers/clk/qcom/gcc-ipq806x.c
> @@ -291,13 +291,13 @@ static const char * const gcc_pxo_pll3[] = {
> "pll3",
> };
>
> -static const struct parent_map gcc_pxo_pll8_pll0[] = {
> +static const struct parent_map gcc_pxo_pll8_pll0_map[] = {
> { P_PXO, 0 },
> { P_PLL8, 3 },
> { P_PLL0, 2 }
> };
>
> -static const char * const gcc_pxo_pll8_pll0_map[] = {
> +static const char * const gcc_pxo_pll8_pll0[] = {
> "pxo",
> "pll8_vote",
> "pll0_vote",
> @@ -1993,7 +1993,7 @@ static struct clk_rcg usb30_master_clk_src = {
> },
> .s = {
> .src_sel_shift = 0,
> - .parent_map = gcc_pxo_pll8_pll0,
> + .parent_map = gcc_pxo_pll8_pll0_map,
> },
> .freq_tbl = clk_tbl_usb30_master,
> .clkr = {
> @@ -2001,7 +2001,7 @@ static struct clk_rcg usb30_master_clk_src = {
> .enable_mask = BIT(11),
> .hw.init = &(struct clk_init_data){
> .name = "usb30_master_ref_src",
> - .parent_names = gcc_pxo_pll8_pll0_map,
> + .parent_names = gcc_pxo_pll8_pll0,
> .num_parents = 3,
> .ops = &clk_rcg_ops,
> .flags = CLK_SET_RATE_GATE,
> @@ -2063,7 +2063,7 @@ static struct clk_rcg usb30_utmi_clk = {
> },
> .s = {
> .src_sel_shift = 0,
> - .parent_map = gcc_pxo_pll8_pll0,
> + .parent_map = gcc_pxo_pll8_pll0_map,
> },
> .freq_tbl = clk_tbl_usb30_utmi,
> .clkr = {
> @@ -2071,7 +2071,7 @@ static struct clk_rcg usb30_utmi_clk = {
> .enable_mask = BIT(11),
> .hw.init = &(struct clk_init_data){
> .name = "usb30_utmi_clk",
> - .parent_names = gcc_pxo_pll8_pll0_map,
> + .parent_names = gcc_pxo_pll8_pll0,
> .num_parents = 3,
> .ops = &clk_rcg_ops,
> .flags = CLK_SET_RATE_GATE,
> @@ -2133,7 +2133,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = {
> },
> .s = {
> .src_sel_shift = 0,
> - .parent_map = gcc_pxo_pll8_pll0,
> + .parent_map = gcc_pxo_pll8_pll0_map,
> },
> .freq_tbl = clk_tbl_usb,
> .clkr = {
> @@ -2141,7 +2141,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = {
> .enable_mask = BIT(11),
> .hw.init = &(struct clk_init_data){
> .name = "usb_hs1_xcvr_src",
> - .parent_names = gcc_pxo_pll8_pll0_map,
> + .parent_names = gcc_pxo_pll8_pll0,
> .num_parents = 3,
> .ops = &clk_rcg_ops,
> .flags = CLK_SET_RATE_GATE,
> @@ -2197,7 +2197,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = {
> },
> .s = {
> .src_sel_shift = 0,
> - .parent_map = gcc_pxo_pll8_pll0,
> + .parent_map = gcc_pxo_pll8_pll0_map,
> },
> .freq_tbl = clk_tbl_usb,
> .clkr = {
> @@ -2205,7 +2205,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = {
> .enable_mask = BIT(11),
> .hw.init = &(struct clk_init_data){
> .name = "usb_fs1_xcvr_src",
> - .parent_names = gcc_pxo_pll8_pll0_map,
> + .parent_names = gcc_pxo_pll8_pll0,
> .num_parents = 3,
> .ops = &clk_rcg_ops,
> .flags = CLK_SET_RATE_GATE,
> --
> 2.34.1
>
