From: fugang.duan@xxxxxxxxxxxxx > >From: Frank Li > >> From: Fugang Duan <B38611@xxxxxxxxxxxxx> > >> > >> Since enet-avb has 64 bytes alignment limitation for rx DMA transfer. > >> The previous enet IP for ARM platform has 16 bytes alignment for tx > >> DMA transfer. > > > >Do you mean rx or tx here? or both?? > > > >And can we beat up the hardware designers to stop these restrictions on rx > >(in particular) ethernet buffer alignments? > >A device isn't suitable for ethernet unless is can write the destination > >mac address to a 4n+2 boundary. > > > > David > > > Hi, David, > > For previous enet IP there has 16 bytes data buffer alignment limitation for tx & rx DMA transfer. > For imx6sx enet-avb IP, there has 64 bytes data buffer alignment limitation for rx DMA transfer, byte > alignment for tx data > Buffer for DMA transfer. > > I think rx data buffer alignment limitation don't introduce performance drop, is not complex for sw > implemention. Anyway, > We can request IC designer to remove the limitation for future chips. The 'problem' is that you need the IP header to be 32bit aligned. If the dma buffer has to be aligned then the code either has to do an expensive misaligned copy of the entire frame (at some point the entire frame is almost certainly all copied into an aligned buffer), or take the hit of misaligned memory accesses (which might have to be emulated with byte transfers). The rx buffer can be aligned provided the hardware skips (or writes junk to) the first two bytes. David -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
