On Mon, Aug 11, 2014 at 12:48:08PM +0530, Priyanka Jain wrote:
> T1040/T1042RDB is Freescale Reference Design Board.
> The board can support both T1040/T1042 QorIQ Power Architecture™ processor.
>
> T1040/T1042RDB board Overview
> -----------------------
> - SERDES Connections, 8 lanes supporting:
> - PCI
> - SGMII
> - QSGMII
> - SATA 2.0
> - DDR Controller
> - Supports rates of up to 1600 MHz data-rate
> - Supports one DDR3LP UDIMM
> -IFC/Local Bus
> - NAND flash: 1GB 8-bit NAND flash
> - NOR: 128MB 16-bit NOR Flash
> - Ethernet
> - Two on-board RGMII 10/100/1G ethernet ports.
> - PHY #0 remains powered up during deep-sleep
> - CPLD
> - Clocks
> - System and DDR clock (SYSCLK, “DDRCLK”)
> - SERDES clocks
> - Power Supplies
> - USB
> - Supports two USB 2.0 ports with integrated PHYs
> - Two type A ports with 5V@1.5A per port.
> - SDHC
> - SDHC/SDXC connector
> - SPI
> - On-board 64MB SPI flash
> - I2C
> - Devices connected: EEPROM, thermal monitor, VID controller
> - Other IO
> - Two Serial ports
> - ProfiBus port
>
> Add support for T1040/T1042 RDB board:
> -add device tree
> -add entry in Kconfig to build
> -Add entry in corenet_generic.c, as it is similar to other corenet platforms
>
> Signed-off-by: Priyanka Jain <Priyanka.Jain@xxxxxxxxxxxxx>
> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@xxxxxxxxxxxxx>
> Signed-off-by: Prabhakar Kushwaha <prabhakar@xxxxxxxxxxxxx>
> ---
> changes for v3: Incorporated Scott comments on moving cpld compatible
> field to board specific file as cpld binaries are different
[snip]
> diff --git a/arch/powerpc/boot/dts/t1042rdb.dts b/arch/powerpc/boot/dts/t1042rdb.dts
> new file mode 100644
> index 0000000..228a635
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/t1042rdb.dts
[snip]
> +/include/ "fsl/t104xsi-pre.dtsi"
> +/include/ "t104xrdb.dtsi"
> +
> +/ {
> + model = "fsl,T1042RDB";
> + compatible = "fsl,T1042RDB";
> + ifc: localbus@ffe124000 {
> + cpld@3,0 {
> + compatible = "fsl,t1040rdb-cpld";
> + };
> + };
> +};
The point of moving the cpld compatible is so that they can match the
exact CPLD binary being used. The above does not match.
Likewise in patch 2/2
-Scott
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