Background firstly, EMMC and NAND has the same clock control register named 'SD_EMMC_CLOCK' which is defined in EMMC port internally. bit0~5 of 'SD_EMMC_CLOCK' is the divider and bit6~7 is the mux for fix pll and xtal. Previously a common MMC sub clock framework is implemented and shared by EMMC and NAND, but that is coupling the EMMC and NAND, although EMMC and NAND is mutually exclusive. see the link: [https://lore.kernel.org/all/1jy23226sa.fsf@xxxxxxxxxxxxxxxxxxxxxxxxxxxxx/] Now we plan to abandon common mmc sub clock framework and recovery the series. Changes since v1 [2] - use clk_parent_data instead of parent_names - define a reg resource instead of sd_emmc_c_clkc [1] https://lore.kernel.org/r/20220106033130.37623-1-liang.yang@xxxxxxxxxxx https://lore.kernel.org/r/20220106032504.23310-1-liang.yang@xxxxxxxxxxx Liang Yang (2): mtd: rawnand: meson: discard the common MMC sub clock framework dt-bindings: nand: meson: refine Amlogic NAND controller driver .../bindings/mtd/amlogic,meson-nand.txt | 60 ---------- .../bindings/mtd/amlogic,meson-nand.yaml | 70 ++++++++++++ drivers/mtd/nand/raw/meson_nand.c | 107 ++++++++++-------- 3 files changed, 131 insertions(+), 106 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt create mode 100644 Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml -- 2.34.1
