On Mon, Feb 14, 2022 at 12:06 PM Heiko Stübner <heiko@xxxxxxxxx> wrote: > > Am Donnerstag, 10. Februar 2022, 22:40:16 CET schrieb Atish Patra: > > Multi-letter extensions can be probed using exising > > riscv_isa_extension_available API now. It doesn't support versioning > > right now as there is no use case for it. > > Individual extension specific implementation will be added during > > each extension support. > > > > Signed-off-by: Atish Patra <atishp@xxxxxxxxxxxx> > > Tested-by: Heiko Stuebner <heiko@xxxxxxxxx> > > > By the way, does a similar parsing exist for opensbi as well? > Things like svpbmt as well as zicbom have CSR bits controlling how > these functions should behave (enabling them, etc), so I guess > opensbi also needs to parse the extensions from the ISA string? > > No. Currently, OpenSBI relies on the CSR read/write & trap method to identify the extensions [1]. https://github.com/riscv-software-src/opensbi/blob/master/lib/sbi/sbi_hart.c#L404 In the future, zicbom can be detected in the same manner. However, svpbmt is a bit tricky as it doesn't define any new CSR. Do you think OpenSBI needs to detect svpbmt for any reason ? > Heiko > > > --- > > arch/riscv/include/asm/hwcap.h | 18 ++++++++++++++++++ > > arch/riscv/kernel/cpufeature.c | 27 ++++++++++++++++++++++++--- > > 2 files changed, 42 insertions(+), 3 deletions(-) > > > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > > index 5ce50468aff1..170bd80da520 100644 > > --- a/arch/riscv/include/asm/hwcap.h > > +++ b/arch/riscv/include/asm/hwcap.h > > @@ -34,7 +34,25 @@ extern unsigned long elf_hwcap; > > #define RISCV_ISA_EXT_s ('s' - 'a') > > #define RISCV_ISA_EXT_u ('u' - 'a') > > > > +/* > > + * Increse this to higher value as kernel support more ISA extensions. > > + */ > > #define RISCV_ISA_EXT_MAX 64 > > +#define RISCV_ISA_EXT_NAME_LEN_MAX 32 > > + > > +/* The base ID for multi-letter ISA extensions */ > > +#define RISCV_ISA_EXT_BASE 26 > > + > > +/* > > + * This enum represent the logical ID for each multi-letter RISC-V ISA extension. > > + * The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed > > + * RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter > > + * extensions while all the multi-letter extensions should define the next > > + * available logical extension id. > > + */ > > +enum riscv_isa_ext_id { > > + RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, > > +}; > > > > unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); > > > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > > index e9e3b0693d16..469b9739faf7 100644 > > --- a/arch/riscv/kernel/cpufeature.c > > +++ b/arch/riscv/kernel/cpufeature.c > > @@ -83,7 +83,7 @@ void __init riscv_fill_hwcap(void) > > > > for_each_of_cpu_node(node) { > > unsigned long this_hwcap = 0; > > - unsigned long this_isa = 0; > > + uint64_t this_isa = 0; > > > > if (riscv_of_processor_hartid(node) < 0) > > continue; > > @@ -169,12 +169,22 @@ void __init riscv_fill_hwcap(void) > > if (*isa != '_') > > --isa; > > > > +#define SET_ISA_EXT_MAP(name, bit) \ > > + do { \ > > + if ((ext_end - ext == sizeof(name) - 1) && \ > > + !memcmp(ext, name, sizeof(name) - 1)) { \ > > + this_isa |= (1UL << bit); \ > > + pr_info("Found ISA extension %s", name);\ > > + } \ > > + } while (false) \ > > + > > if (unlikely(ext_err)) > > continue; > > if (!ext_long) { > > this_hwcap |= isa2hwcap[(unsigned char)(*ext)]; > > this_isa |= (1UL << (*ext - 'a')); > > } > > +#undef SET_ISA_EXT_MAP > > } > > > > /* > > @@ -187,10 +197,21 @@ void __init riscv_fill_hwcap(void) > > else > > elf_hwcap = this_hwcap; > > > > - if (riscv_isa[0]) > > + if (riscv_isa[0]) { > > +#if IS_ENABLED(CONFIG_32BIT) > > + riscv_isa[0] &= this_isa & 0xFFFFFFFF; > > + riscv_isa[1] &= this_isa >> 32; > > +#else > > riscv_isa[0] &= this_isa; > > - else > > +#endif > > + } else { > > +#if IS_ENABLED(CONFIG_32BIT) > > + riscv_isa[0] = this_isa & 0xFFFFFFFF; > > + riscv_isa[1] = this_isa >> 32; > > +#else > > riscv_isa[0] = this_isa; > > +#endif > > + } > > } > > > > /* We don't support systems with F but without D, so mask those out > > > > > > -- Regards, Atish
