On Thu, Jan 27, 2022 at 04:10:51PM +0200, Abel Vesa wrote: > The audio_mclk_root_clk was added as a gate with the CCGR121 (0x4790), > but according to the reference manual, there is no such gate. Moreover, > the consumer driver of the mentioned clock might gate it and leave > the ECSPI2 (the true owner of that gate) hanging. So lets use the > audio_mclk_post_div, which is the parent. > > Signed-off-by: Abel Vesa <abel.vesa@xxxxxxx> Applied, thanks!
