Add AMP enable node and pinmux for primary and secondary I2S
for SC7280 based platforms.
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@xxxxxxxxxxx>
Co-developed-by: Venkata Prasad Potturu <quic_potturu@xxxxxxxxxxx>
Signed-off-by: Venkata Prasad Potturu <quic_potturu@xxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 41 +++++++++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 42 ++++++++++++++++++++++++++++++++
2 files changed, 83 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index d623d71..1a9b465 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -437,6 +437,26 @@
};
};
+&pri_mi2s_data0 {
+ drive-strength = <6>;
+};
+
+&pri_mi2s_data1 {
+ drive-strength = <6>;
+};
+
+&pri_mi2s_mclk {
+ drive-strength = <6>;
+};
+
+&pri_mi2s_sclk {
+ drive-strength = <6>;
+};
+
+&pri_mi2s_ws {
+ drive-strength = <6>;
+};
+
&qspi_cs0 {
bias-disable;
};
@@ -490,7 +510,28 @@
bias-pull-up;
};
+&sec_mi2s_data0 {
+ drive-strength = <6>;
+ bias-disable;
+};
+
+&sec_mi2s_sclk {
+ drive-strength = <6>;
+ bias-disable;
+};
+
+&sec_mi2s_ws {
+ drive-strength = <6>;
+};
+
&tlmm {
+ amp_en: amp-en {
+ pins = "gpio63";
+ function = "gpio";
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+
nvme_pwren: nvme-pwren {
function = "gpio";
};
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 937c2e0..503d461 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -3461,6 +3461,32 @@
};
};
+ pri_mi2s_data0: pri-mi2s-data0 {
+ pins = "gpio98";
+ function = "mi2s0_data0";
+ };
+
+ pri_mi2s_data1: pri-mi2s-data1 {
+ pins = "gpio99";
+ function = "mi2s0_data1";
+ };
+
+ pri_mi2s_mclk: pri-mi2s-mclk {
+ pins = "gpio96";
+ function = "pri_mi2s";
+ };
+
+ pri_mi2s_sclk: pri-mi2s-sclk {
+ pins = "gpio97";
+ function = "mi2s0_sck";
+ };
+
+ pri_mi2s_ws: pri-mi2s-ws {
+ pins = "gpio100";
+ function = "mi2s0_ws";
+ };
+
+
qup_uart8_cts: qup-uart8-cts {
pins = "gpio32";
function = "qup10";
@@ -3620,6 +3646,22 @@
pins = "gpio63";
function = "qup17";
};
+
+ sec_mi2s_data0: sec-mi2s-data0 {
+ pins = "gpio107";
+ function = "mi2s1_data0";
+ };
+
+ sec_mi2s_sclk: sec-mi2s-sclk {
+ pins = "gpio106";
+ function = "mi2s1_sck";
+ };
+
+ sec_mi2s_ws: sec-mi2s-ws {
+ pins = "gpio108";
+ function = "mi2s1_ws";
+ };
+
};
imem@146a5000 {
--
2.7.4
