On 2022-02-08 13:18, Vignesh Raghavendra wrote:
The AM62 SoC family is the follow on AM335x built on K3 Multicore SoC
architecture platform, providing ultra-low-power modes, dual display,
multi-sensor edge compute, security and other BOM-saving integration.
The AM62 SoC targets broad market to enable applications such as
Industrial HMI, PLC/CNC/Robot control, Medical Equipment, Building
Automation, Appliances and more.
Some highlights of this SoC are:
* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster.
Pin-to-pin compatible options for single and quad core are available.
* Cortex-M4F for general-purpose or safety usage.
* Dual display support, providing 24-bit RBG parallel interface and
OLDI/LVDS-4 Lane x2, up to 200MHz pixel clock support for 2K display
resolution.
* Selectable GPUsupport, up to 8GFLOPS, providing better user
experience
in 3D graphic display case and Android.
* PRU(Programmable Realtime Unit) support for customized programmable
interfaces/IOs.
* Integrated Giga-bit Ethernet switch supporting up to a total of two
external ports (TSN capable).
* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for
NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio,
1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals.
* Dedicated Centralized System Controller for Security, Power, and
Resource Management.
* Multiple low power modes support, ex: Deep sleep,Standby, MCU-only,
enabling battery powered system design.
This add bare minimum DT describing ARM compute clusters, Main, MCU and
Wakeup domain and interconnects, UARTs and I2Cs to enable booting using
ramdisk.
More details can be found in the Technical Reference Manual:
https://www.ti.com/lit/pdf/spruiv7
Co-developed-by: Suman Anna <s-anna@xxxxxx>
Signed-off-by: Suman Anna <s-anna@xxxxxx>
Co-developed-by: Nishanth Menon <nm@xxxxxx>
Signed-off-by: Nishanth Menon <nm@xxxxxx>
Signed-off-by: Vignesh Raghavendra <vigneshr@xxxxxx>
---
arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 263 +++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi | 36 +++
arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 41 ++++
arch/arm64/boot/dts/ti/k3-am62.dtsi | 104 ++++++++
arch/arm64/boot/dts/ti/k3-am625.dtsi | 103 ++++++++
5 files changed, 547 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-am62-main.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-am62.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-am625.dtsi
diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
new file mode 100644
index 000000000000..81d6d99ca180
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
@@ -0,0 +1,263 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM625 SoC Family Main Domain peripherals
+ *
+ * Copyright (C) 2020-2022 Texas Instruments Incorporated -
https://www.ti.com/
+ */
+
+&cbass_main {
+ gic500: interrupt-controller@1800000 {
+ compatible = "arm,gic-v3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
+ <0x00 0x01880000 0x00 0xC0000>; /* GICR */
Usual rant: you are missing the GICC, GICH and GICV regions
that are implemented by the CPU. Cortex-A53 implements them
(they are not optional), so please describe them.
+ /*
+ * vcpumntirq:
+ * virtual CPU interface maintenance interrupt
+ */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ gic_its: msi-controller@1820000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x00 0x01820000 0x00 0x10000>;
+ socionext,synquacer-pre-its = <0x1000000 0x400000>;
The mind boggles...
M.
--
Jazz is not dead. It just smells funny...
