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> On Wed, Feb 9, 2022 at 10:02 AM <Kavyasree.Kotagiri@xxxxxxxxxxxxx>
> wrote:
> > > > On 13/01/2022 at 09:00, Kavyasree Kotagiri wrote:
>
> > > > > +&gpio {
> > > > > + fc_shrd7_pins: fc_shrd7-pins {
> > > > > + pins = "GPIO_49";
> > > > > + function = "fc_shrd7";
> > > > > + };
> > >
> > > These properties don't look like most pinctrl nodes, has the binding
> > > been reviewed?
> > > I don't see it in Documentation/devicetree/bindings/pinctrl/
> > >
> > This is similar to the ones used in Microchip Ocelot and Sparx5 pinctrl.
> > For example, see usart_pins of gpio nodes in below links:
> > https://sbexr.rabexc.org/latest/sources//84/d39b543790ff25.jhtml
> >
> https://searchcode.com/file/333750634/arch/mips/boot/dts/mscc/ocelot.dt
> si/
>
> Ok, I see, so this was reviewed by both Rob and LinusW, I assume it's fine
> then, though the use of strings with capital letters, with all pins
> named "GPIO_*"
> still looks odd.
>
> For my understanding, would you describe the lan966x family as
> a follow-up to Ocelot, with the CPU cores replaced and flexcom added,
> or should I think of it as a SAMA7 based SoC design that incorporates
> the Vitesse switch IP?
>
No, Only GPIO controller block is similar to the one on Ocelot board and FireAnt platforms.
Only difference is LAN966 pinctrl supports 8 ALT modes for which it requires three
ALT registers to be configured. Whereas, ocelot and Fireant support 4 ALT modes.
> Arnd
