Re: [PATCH v2] add pmu to amlogic meson sm1

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On 2022-02-07 08:14, Neil Armstrong wrote:
Hi,

On 06/02/2022 15:43, Benjamin Mordaunt wrote:
---
The dts for meson sm1 appears to omit the SoC's PMU,
which is essential for accessing perf events regarding
e.g. cache on e.g. the Odroid C4 platform. Add it.

  arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 13 ++++++++++++-
  1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
index 3d8b1f4f2..4147eecd2 100644
--- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
@@ -6,6 +6,8 @@
  #include "meson-g12-common.dtsi"
  #include <dt-bindings/clock/axg-audio-clkc.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
  #include <dt-bindings/power/meson-sm1-power.h>
  #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
  #include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h>
@@ -90,7 +92,16 @@ l2: l2-cache0 {
              compatible = "cache";
          };
      };
-
+
+    arm-pmu {
+        compatible = "arm,cortex-a55-pmu";
+        interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+                 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+                 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+                 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+    };
+
      cpu_opp_table: opp-table {
          compatible = "operating-points-v2";
          opp-shared;

Please see Marc's comments about PMU support:
http://lore.kernel.org/r/8735pcq63o.wl-maz@xxxxxxxxxx

If SM1 actually has distinct per-core interrupts as the patch implies then it's fine - it's only G12B and anything else that combines multiple PMU IRQs into a single SPI which are unsupportable.

Robin.



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