On SM8450 platform PCIe hosts do not use all the clocks (and add several
additional clocks), so expand the driver to handle these requirements.
PCIe0 and PCIe1 hosts use different sets of clocks, so separate entries
are required.
Reviewed-by: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
---
drivers/pci/controller/dwc/pcie-qcom.c | 55 ++++++++++++++++++++------
1 file changed, 42 insertions(+), 13 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 6034a933814d..174a650ffbbb 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -160,7 +160,7 @@ struct qcom_pcie_resources_2_3_3 {
/* 6 clocks typically, 7 for sm8250 */
struct qcom_pcie_resources_2_7_0 {
- struct clk_bulk_data clks[7];
+ struct clk_bulk_data clks[9];
int num_clks;
struct regulator_bulk_data supplies[2];
struct reset_control *pci_reset;
@@ -189,7 +189,10 @@ struct qcom_pcie_ops {
struct qcom_pcie_cfg {
const struct qcom_pcie_ops *ops;
+ bool has_tbu_clk;
bool has_ddrss_sf_tbu_clk;
+ bool has_aggre0_clk;
+ bool has_aggre1_clk;
};
struct qcom_pcie {
@@ -1113,6 +1116,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
struct dw_pcie *pci = pcie->pci;
struct device *dev = pci->dev;
+ unsigned int idx;
int ret;
res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
@@ -1126,18 +1130,22 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
if (ret)
return ret;
- res->clks[0].id = "aux";
- res->clks[1].id = "cfg";
- res->clks[2].id = "bus_master";
- res->clks[3].id = "bus_slave";
- res->clks[4].id = "slave_q2a";
- res->clks[5].id = "tbu";
- if (pcie->cfg->has_ddrss_sf_tbu_clk) {
- res->clks[6].id = "ddrss_sf_tbu";
- res->num_clks = 7;
- } else {
- res->num_clks = 6;
- }
+ idx = 0;
+ res->clks[idx++].id = "aux";
+ res->clks[idx++].id = "cfg";
+ res->clks[idx++].id = "bus_master";
+ res->clks[idx++].id = "bus_slave";
+ res->clks[idx++].id = "slave_q2a";
+ if (pcie->cfg->has_tbu_clk)
+ res->clks[idx++].id = "tbu";
+ if (pcie->cfg->has_ddrss_sf_tbu_clk)
+ res->clks[idx++].id = "ddrss_sf_tbu";
+ if (pcie->cfg->has_aggre0_clk)
+ res->clks[idx++].id = "aggre0";
+ if (pcie->cfg->has_aggre1_clk)
+ res->clks[idx++].id = "aggre1";
+
+ res->num_clks = idx;
ret = devm_clk_bulk_get(dev, res->num_clks, res->clks);
if (ret < 0)
@@ -1178,6 +1186,9 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
goto err_disable_clocks;
}
+ /* Wait for reset to complete, required on SM8450 */
+ usleep_range(1000, 1500);
+
/* configure PCIe to RC mode */
writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
@@ -1427,15 +1438,31 @@ static const struct qcom_pcie_cfg ipq4019_cfg = {
static const struct qcom_pcie_cfg sdm845_cfg = {
.ops = &ops_2_7_0,
+ .has_tbu_clk = true,
};
static const struct qcom_pcie_cfg sm8250_cfg = {
+ .ops = &ops_1_9_0,
+ .has_tbu_clk = true,
+ .has_ddrss_sf_tbu_clk = true,
+};
+
+static const struct qcom_pcie_cfg sm8450_pcie0_cfg = {
+ .ops = &ops_1_9_0,
+ .has_ddrss_sf_tbu_clk = true,
+ .has_aggre0_clk = true,
+ .has_aggre1_clk = true,
+};
+
+static const struct qcom_pcie_cfg sm8450_pcie1_cfg = {
.ops = &ops_1_9_0,
.has_ddrss_sf_tbu_clk = true,
+ .has_aggre1_clk = true,
};
static const struct qcom_pcie_cfg sc7280_cfg = {
.ops = &ops_1_9_0,
+ .has_tbu_clk = true,
};
static const struct dw_pcie_ops dw_pcie_ops = {
@@ -1541,6 +1568,8 @@ static const struct of_device_id qcom_pcie_match[] = {
{ .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg },
{ .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg },
{ .compatible = "qcom,pcie-sc8180x", .data = &sm8250_cfg },
+ { .compatible = "qcom,pcie-sm8450-pcie0", .data = &sm8450_pcie0_cfg },
+ { .compatible = "qcom,pcie-sm8450-pcie1", .data = &sm8450_pcie1_cfg },
{ .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg },
{ }
};
--
2.34.1
