> 31.01.2022 18:38, Akhil R пишет:
> > Does the below method look good? bytes_xfer is updated on every ISR and in
> > tx_status(), the wcount is read to calculate the intermittent value. If the
> transfer
> > get complete in between, use wcount as 0 to add sg_req.len to bytes_xfer
> >
> > static int tegra_dma_get_residual(struct tegra_dma_channel *tdc)
> > {
> > unsigned long wcount = 0, status;
> > unsigned int bytes_xfer, residual;
> > struct tegra_dma_desc *dma_desc = tdc->dma_desc;
> > struct tegra_dma_sg_req *sg_req = dma_desc->sg_req;
> >
> > /*
> > * Do not read from CHAN_XFER_COUNT if EOC bit is set
> > * as the transfer would have already completed and
> > * the register could have updated for next transfer
> > * in case of cyclic transfers.
> > */
> > status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
> > if (!(status & TEGRA_GPCDMA_STATUS_ISE_EOC))
> > wcount = tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT);
>
> You can't read WCOUNT after the STATUS without racing with the STATUS
> updates made by h/w. You should read the WCOUNT first and only then
> check the STATUS.
>
> You should also check whether T20 tegra_dma_sg_bytes_xferred()
> workarounds apply to newer h/w. I see that the h/w base hasn't changed
> much since T20.
The calculation in T20 driver is not applicable here. The register shows the
actual number of words remaining to be transferred as far as I understand.
Thanks,
Akhil
