Hi,
On Sun, Jan 30, 2022 at 05:03:24PM -0500, Jesse Taube wrote:
> Add mmc0 and 1 for f1c100s dtsi.
>
> Signed-off-by: Jesse Taube <Mr.Bossman075@xxxxxxxxx>
> ---
> V1 -> V2:
> * Split patch
> ---
> arch/arm/boot/dts/suniv-f1c100s.dtsi | 41 ++++++++++++++++++++++++++++
> 1 file changed, 41 insertions(+)
>
> diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> index 953228cc8d52..60fa56c278a8 100644
> --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> @@ -96,6 +96,11 @@ uart0_pe_pins: uart0-pe-pins {
> pins = "PE0", "PE1";
> function = "uart0";
> };
> +
> + mmc0_pins: mmc0-pins {
> + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
> + function = "mmc0";
> + };
Pinctrl nodes are ordered alphabetically
Also, you need to have a drive-strength of 30mA
> };
>
> timer@1c20c00 {
> @@ -111,6 +116,42 @@ wdt: watchdog@1c20ca0 {
> reg = <0x01c20ca0 0x20>;
> };
>
> + mmc0: mmc@1c0f000 {
> + compatible = "allwinner,suniv-f1c100s-mmc",
> + "allwinner,sun7i-a20-mmc";
> + reg = <0x01c0f000 0x1000>;
> + clocks = <&ccu CLK_BUS_MMC0>,
> + <&ccu CLK_MMC0>,
> + <&ccu CLK_MMC0_OUTPUT>,
> + <&ccu CLK_MMC0_SAMPLE>;
> + clock-names = "ahb", "mmc", "output", "sample";
> + resets = <&ccu RST_BUS_MMC0>;
> + reset-names = "ahb";
> + interrupts = <23>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc0_pins>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mmc1: mmc@1c10000 {
> + compatible = "allwinner,suniv-f1c100s-mmc",
> + "allwinner,sun7i-a20-mmc";
> + reg = <0x01c10000 0x1000>;
> + clocks = <&ccu CLK_BUS_MMC1>,
> + <&ccu CLK_MMC1>,
> + <&ccu CLK_MMC1_OUTPUT>,
> + <&ccu CLK_MMC1_SAMPLE>;
> + clock-names = "ahb", "mmc", "output", "sample";
> + resets = <&ccu RST_BUS_MMC1>;
> + reset-names = "ahb";
> + interrupts = <24>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
And here, the nodes are ordered by register base address
Maxime
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