30.01.2022 13:05, Dmitry Osipenko пишет: > static int tegra_dma_device_resume(struct dma_chan *dc) > { > struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); > u32 val; > > if (!tdc->tdma->chip_data->hw_support_pause) > return -ENOSYS; > > if (!tdc->dma_desc) > return 0; > > val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE); > val &= ~TEGRA_GPCDMA_CHAN_CSRE_PAUSE; > tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, val); > > enable_irq(tdc->irq); Correction: if (tdc->dma_desc) { val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE); val &= ~TEGRA_GPCDMA_CHAN_CSRE_PAUSE; tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, val); } enable_irq(tdc->irq);