On Fri, Jan 28, 2022 at 2:37 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote: > > To improve human readability and enable automatic validation, the tuples > in "interrupts-extended" properties should be grouped using angle > brackets. > > Signed-off-by: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> > Reviewed-by: Rob Herring <robh@xxxxxxxxxx> Looks good to me. Reviewed-by: Anup Patel <anup@xxxxxxxxxxxxxx> Regards, Anup > --- > v4: > - Add Reviewed-by (this time for real ;-), > > v3: > - Add Reviewed-by, > > v2: > - Split in two patches. > --- > Documentation/devicetree/bindings/timer/sifive,clint.yaml | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > index fe4b73c3f269fc0f..e64f46339079fa3f 100644 > --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > @@ -57,10 +57,10 @@ examples: > - | > timer@2000000 { > compatible = "sifive,fu540-c000-clint", "sifive,clint0"; > - interrupts-extended = <&cpu1intc 3 &cpu1intc 7 > - &cpu2intc 3 &cpu2intc 7 > - &cpu3intc 3 &cpu3intc 7 > - &cpu4intc 3 &cpu4intc 7>; > + interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>, > + <&cpu2intc 3>, <&cpu2intc 7>, > + <&cpu3intc 3>, <&cpu3intc 7>, > + <&cpu4intc 3>, <&cpu4intc 7>; > reg = <0x2000000 0x10000>; > }; > ... > -- > 2.25.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@xxxxxxxxxxxxxxxxxxx > http://lists.infradead.org/mailman/listinfo/linux-riscv