From: Lin Huang <hl@xxxxxxxxxxxxxx> These are required to support DDR DVFS on RK3399 platforms. Signed-off-by: Lin Huang <hl@xxxxxxxxxxxxxx> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@xxxxxxxxxxxxx> Signed-off-by: Gaël PORTAY <gael.portay@xxxxxxxxxxxxx> Signed-off-by: Daniel Lezcano <daniel.lezcano@xxxxxxxxxx> Signed-off-by: Brian Norris <briannorris@xxxxxxxxxxxx> Change since Daniel's posting: reordered by unit address, per existing style --- Changes in v2: - rename dmc to memory-controller Changes in v1: This is based on a v5 posting from various authors: https://lore.kernel.org/lkml/20210308233858.24741-3-daniel.lezcano@xxxxxxxxxx/ Much of that series was already merged, so I start over with the numbering. arch/arm64/boot/dts/rockchip/rk3399.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index d3cdf6f42a30..4096ef6f7b72 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1295,6 +1295,25 @@ pwm3: pwm@ff420030 { status = "disabled"; }; + dfi: dfi@ff630000 { + reg = <0x00 0xff630000 0x00 0x4000>; + compatible = "rockchip,rk3399-dfi"; + rockchip,pmu = <&pmugrf>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru PCLK_DDR_MON>; + clock-names = "pclk_ddr_mon"; + status = "disabled"; + }; + + dmc: memory-controller { + compatible = "rockchip,rk3399-dmc"; + rockchip,pmu = <&pmugrf>; + devfreq-events = <&dfi>; + clocks = <&cru SCLK_DDRC>; + clock-names = "dmc_clk"; + status = "disabled"; + }; + vpu: video-codec@ff650000 { compatible = "rockchip,rk3399-vpu"; reg = <0x0 0xff650000 0x0 0x800>; -- 2.35.0.rc0.227.g00780c9af4-goog
