Re: [PATCH 21/27] arm64: dts: rockchip: rk356x: Add HDMI nodes

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On 2022-01-26 18:44, Peter Geis wrote:
On Wed, Jan 26, 2022 at 12:56 PM Robin Murphy <robin.murphy@xxxxxxx> wrote:

On 2022-01-26 16:04, Peter Geis wrote:
On Wed, Jan 26, 2022 at 9:58 AM Sascha Hauer <s.hauer@xxxxxxxxxxxxxx> wrote:

Add support for the HDMI port found on RK3568.

Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
---
   arch/arm64/boot/dts/rockchip/rk356x.dtsi | 37 +++++++++++++++++++++++-
   1 file changed, 36 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 4008bd666d01..e38fb223e9b8 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -10,7 +10,6 @@
   #include <dt-bindings/pinctrl/rockchip.h>
   #include <dt-bindings/power/rk3568-power.h>
   #include <dt-bindings/soc/rockchip,boot-mode.h>
-#include <dt-bindings/soc/rockchip,vop2.h>
   #include <dt-bindings/thermal/thermal.h>

   / {
@@ -502,6 +501,42 @@ vop_mmu: iommu@fe043e00 {
                  status = "disabled";
          };

+       hdmi: hdmi@fe0a0000 {
+               compatible = "rockchip,rk3568-dw-hdmi";
+               reg = <0x0 0xfe0a0000 0x0 0x20000>;
+               interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru PCLK_HDMI_HOST>,
+                        <&cru CLK_HDMI_SFR>,
+                        <&cru CLK_HDMI_CEC>,
+                        <&pmucru CLK_HDMI_REF>,
+                        <&cru HCLK_VOP>;
+               clock-names = "iahb", "isfr", "cec", "ref", "hclk";
+               pinctrl-names = "default";
+               pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;

I looked into CEC support here, and it seems that it does work with one change.
Please add the two following lines to your patch:
assigned-clocks = <&cru CLK_HDMI_CEC>;
assigned-clock-rates = <32768>;

The issue is the clk_rtc32k_frac clock that feeds clk_rtc_32k which
feeds clk_hdmi_cec is 24mhz at boot, which is too high for CEC to
function.

Wouldn't it make far more sense to just stick a suitable clk_set_rate()
call in the driver? AFAICS it's already explicitly aware of the CEC clock.

This is handled purely in the
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c driver, so I'm hesitant to
touch it there as it would affect all users, not just Rockchip.

I'd have a strong hunch that it's a standard thing for the DesignWare IP and not affected by platform integration. I don't have the magical Synopsys databook, but between the trusty old i.MX6 manual and most of the other in-tree DTs getting their dw-hdmi "cec" clock from suspiciously-obviously-named sources, I'd be somewhat surprised if it was ever anything other than 32KHz.

Robin.

Could someone familiar with the dw-hdmi IP weigh in on the minimum and
maximum clock rate the CEC block can handle?


Robin.

+               power-domains = <&power RK3568_PD_VO>;
+               reg-io-width = <4>;
+               rockchip,grf = <&grf>;
+               #sound-dai-cells = <0>;
+               status = "disabled";
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       hdmi_in: port@0 {
+                               reg = <0>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                       };
+
+                       hdmi_out: port@1 {
+                               reg = <1>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                       };
+               };
+       };
+
          qos_gpu: qos@fe128000 {
                  compatible = "rockchip,rk3568-qos", "syscon";
                  reg = <0x0 0xfe128000 0x0 0x20>;
--
2.30.2


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