Quoting Daniel Mack (2022-01-25 01:33:33) > The CS2000 chip features two input clocks, REF_CLK and CLK_IN. > > In static mode, the output clock (CLK_OUT) is directly derived from > REF_CLK, and CLK_IN is ignored. In dynamic mode, CLK_IN is used by the > digital PLL. > > In dynamic mode, a low-frequency ratio configuration that uses a higher > multiplier factor. > > Until now, only the static mode and high-frequency divider rations of > the hardware was supported by the driver. This patch adds support for > dynamic mode and both ratios: > > * Parse a new OF property 'cirrus,dynamic-mode' to determine the mode > * In dynamic mode, present CLK_IN as parent clock, else use REF_CLK > * The low-frequency ratio mode is automatically selected, depending > on the mode of operation and the given input and output rates > > Signed-off-by: Daniel Mack <daniel@xxxxxxxxxx> > --- Applied to clk-next
