Both the i.MX8MQ and i.MX8MM have G1 and G2 decoders.
The two decoders are similar, but the imx8mm lacks the
post-processor, so they will have distinct compatible flags.
>From what I can tell, the G2 decoder wasn't working, so splitting
the i.MX8MQ VPU into G1 and G2 makes it easier to control them
independently since the TRM of both the i.MX8MQ and
i.MX8MM list them as distinct IP blocks. This also allowed G2 to
become available.
With them being split, the power-domain can shift to the
vpu-blk-ctrl which is available on both i.MX8MQ and i.MX8MM,
but some of bits are different, so they'll have separate bindings.
Lastly, with the G1 and G2 operational, enable the i.MX8MM.
On the i.MX8MM, the clock speed of 600MHz was chosen to match
the default of the kernel repo from NXP and can be overwritten
by board files for anyone who under/over volts the power rail.
There seems to be some disagreement between the TRM and the Datasheet
for the imx8mq as to whether the speed should be 300MHz (TRM) or
600MHz (datasheet), so feedback from NXP would be very much
appreciated.
The repo used as the starting point was:
5.17-rc1
Fluster was run on both i.MX8MM and i.MX8MQ
At 600 MHz, the i.MX8MM had the following:
./fluster.py run -d GStreamer-VP8-V4L2SL-Gst1.0
Ran 55/61 tests successfully in 8.299 secs
./fluster.py run -dGStreamer-H.264-V4L2SL-Gst1.0
Ran 90/135 tests successfully in 71.200 secs
./fluster.py run -d GStreamer-VP9-V4L2SL-Gst1.0
Ran 139/303 tests successfully in 218.079 secs
The i.MX8MQ had the following:
./fluster.py run -d GStreamer-VP8-V4L2SL-Gst1.0
Ran 55/61 tests successfully in 7.732 secs
./fluster.py run -dGStreamer-H.264-V4L2SL-Gst1.0
Ran 90/135 tests successfully in 58.558 secs
./fluster.py run -d GStreamer-VP9-V4L2SL-Gst1.0
Ran 144/303 tests successfully in 271.373 secs
V4: Add a comment and a notice based on feedback from Ezequiel Garcia
if the older compatible flag is used.
Add new patch which removes a reference to vpu from imx8mq-tqma8mq
because the VPU is enabled by default and it's not needed. Without
this change, its device tree would fail to build.
V3: Rebase on 5.17-RC1.
Remove imx8mm-vpu-g2 since it's identical to imx8mq-vpu-g2
Remove unnecessary examples in YAML files.
Remove some unused variables.
V2: Remove references to legacy dt-binding from YAML, but keep
it in the driver so older device trees can still be used.
Fix typos in YAML
Remove reg-names, interrupt-names, and clock-names from YAML,
since each node will only have one of each, they're not necessary
Add Fluster scores to cover letter for i.MX8MQ
Adam Ford (8):
arm64: dts: imx8mq-tqma8mq: Remove redundant vpu reference
dt-bindings: media: nxp, imx8mq-vpu: Split G1 and G2 nodes
media: hantro: Allow i.MX8MQ G1 and G2 to run independently
arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl
arm64: dts: imx8mm: Fix VPU Hanging
dt-bindings: media: nxp, imx8mq-vpu: Add support for G1 on imx8mm
media: hantro: Add support for i.MX8MM Hantro-G1
arm64: dts: imx8mm: Enable Hantro G1 and G2 video decoders
Lucas Stach (3):
dt-bindings: power: imx8mq: add defines for VPU blk-ctrl domains
dt-bindings: soc: add binding for i.MX8MQ VPU blk-ctrl
soc: imx: imx8m-blk-ctrl: add i.MX8MQ VPU blk-ctrl
.../bindings/media/nxp,imx8mq-vpu.yaml | 68 ++++++++----------
.../soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml | 71 +++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 23 +++++-
.../boot/dts/freescale/imx8mq-tqma8mq.dtsi | 4 --
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 63 +++++++++-------
drivers/soc/imx/imx8m-blk-ctrl.c | 66 +++++++++++++++++
drivers/staging/media/hantro/hantro_drv.c | 11 +++
drivers/staging/media/hantro/hantro_hw.h | 2 +
drivers/staging/media/hantro/imx8m_vpu_hw.c | 62 ++++++++++++----
include/dt-bindings/power/imx8mq-power.h | 3 +
10 files changed, 292 insertions(+), 81 deletions(-)
create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml
base-commit: e783362eb54cd99b2cac8b3a9aeac942e6f6ac07
--
2.32.0
