On Mon, Jan 24, 2022 at 09:55:05AM +0100, Frank Wunderlich wrote:
> Hi
>
> > Gesendet: Montag, 24. Januar 2022 um 09:31 Uhr
> > Von: "Sascha Hauer" <sha@xxxxxxxxxxxxxx>
> > An: "Frank Wunderlich" <linux@xxxxxxxxx>
> > Cc: linux-rockchip@xxxxxxxxxxxxxxxxxxx, "Frank Wunderlich" <frank-w@xxxxxxxxxxxxxxx>, "Rob Herring" <robh+dt@xxxxxxxxxx>, "Heiko Stuebner" <heiko@xxxxxxxxx>, "Peter Geis" <pgwipeout@xxxxxxxxx>, "Johan Jonker" <jbx6244@xxxxxxxxx>, devicetree@xxxxxxxxxxxxxxx, linux-arm-kernel@xxxxxxxxxxxxxxxxxxx, linux-kernel@xxxxxxxxxxxxxxx
> > Betreff: Re: [PATCH v2 2/2] arm64: dts: rockchip: Add Bananapi R2 Pro
> >
> > On Sun, Jan 23, 2022 at 02:51:16PM +0100, Frank Wunderlich wrote:
> > > From: Frank Wunderlich <frank-w@xxxxxxxxxxxxxxx>
> > >
> > > This patch adds Devicetree for Bananapi R2 Pro based on RK3568.
> > > Add uart/sd/emmc/i2c/rk809/tsadc nodes for basic function.
> > > Gmac0 is directly connected to wan-port so usable without additional
> > > driver.
> > > On gmac1 there is a switch (rtl8367rb) connected which have not yet a
> > > driver in mainline.
> > >
> > > Patch also prepares nodes for GPIO header.
> > >
> > > Co-developed-by: Peter Geis <pgwipeout@xxxxxxxxx>
> > > Signed-off-by: Peter Geis <pgwipeout@xxxxxxxxx>
> > > Signed-off-by: Frank Wunderlich <frank-w@xxxxxxxxxxxxxxx>
> > > ---
> > > +&gmac0 {
> > > + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
> > > + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
> > > + clock_in_out = "input";
> > > + phy-handle = <&rgmii_phy0>;
> > > + phy-mode = "rgmii";
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&gmac0_miim
> > > + &gmac0_tx_bus2
> > > + &gmac0_rx_bus2
> > > + &gmac0_rgmii_clk
> > > + &gmac0_rgmii_bus>;
> > > +
> > > + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
> > > + snps,reset-active-low;
> > > + /* Reset time is 20ms, 100ms for rtl8211f */
> >
> > Is this really a rtl8211f? I don't know and it could indeed be a
> > rtl8211f, I'm just asking because the comment is copy pasted from
> > the Quartz64 board.
>
> i know thats a RTL8211 phy, but i see no additional letter on the
> chip, based on shematics it's a RTL8211F-CG
Ok. I just wanted to make sure you checked that.
>
> > > + snps,reset-delays-us = <0 20000 100000>;
> > > +
> > > +&mdio0 {
> > > + rgmii_phy0: ethernet-phy@0 {
> > > + compatible = "ethernet-phy-ieee802.3-c22";
> > > + reg = <0x0>;
> > > + };
> >
> > 0 is the broadcast address. I'm not sure if it's a good idea to use it.
> > There should be another address the phy listens on.
>
> took this from the 3568-EVB (like the most parts, as the board is
> mostly the same), and in linux it's the same and working. The switch
> have also phy-id 0 on mdio bus #1, are you sure this is invalid?
It's not invalid, it's just the broadcast address to which other phys
might answer as well. Anyway, as long as there's only a single phy on
the bus it's probably okay.
Sascha
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