From: Jakob Unterwurzacher <jakob.unterwurzacher@xxxxxxxxxxxxxxxxxxxxx>
There are signal integrity issues running the eMMC at 200MHz on Puma
RK3399-Q7.
Similar to the work-around found for RK3399 Gru boards, lowering the
frequency to 100MHz made the eMMC much more stable, so let's lower the
frequency to 100MHz.
It might be possible to run at 150MHz as on RK3399 Gru boards but only
100MHz was extensively tested.
Cc: Quentin Schulz <foss+kernel@xxxxxxxxx>
Signed-off-by: Jakob Unterwurzacher <jakob.unterwurzacher@xxxxxxxxxxxxxxxxxxxxx>
Signed-off-by: Quentin Schulz <quentin.schulz@xxxxxxxxxxxxxxxxxxxxx>
---
Note/RFC: as opposed to gru DTSI, max-frequency is used here instead of
assigned-clock-rates.
AFAIU, max-frequency applies to the SD bus rate, while
assigned-clock-rates applies to the clock fed to the SD host controller
inside the SoC. max-frequency does not interact with the clock subsystem
AFAICT. assigned-clock-rates sets the clock rate at probe, regardless of
eMMC tuning.
Technically, the Arasan SDHC IP supports silicon-hardcoded clock
multiplier so I think setting assigned-clock-rates as a way of rate
limiting the eMMC block is incorrect and max-frequency should be used
instead (as done in this patch). Otherwise the SDHC could still potentially
derive a 200MHz clock from a lower rate clock thanks to its multiplier.
arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
index fb67db4619ea..a6108578aae0 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
@@ -425,6 +425,12 @@ vcc5v0_host_en: vcc5v0-host-en {
};
&sdhci {
+ /*
+ * Signal integrity isn't great at 200MHz but 100MHz has proven stable
+ * enough.
+ */
+ max-frequency = <100000000>;
+
bus-width = <8>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
--
2.34.1
