Jiri Slaby <jirislaby@xxxxxxxxxx> 於 2022年1月13日 週四 下午7:12寫道： > > On 13. 01. 22, 11:56, hammer hsieh wrote: > >> Could you explain me what posted write is and how does it not matter in > >> this case? > >> > > > > Each UART ISC register contains > > No, you still don't follow what I write. Use your favorite web search > for "posted write" and/or consult with your HW team. > Maybe this time, we are on the same page. Our SP7021 chipset is designed on ARM Cortex-A7 Quad core. Register Access through AMBA(AXI bus), and it is non-cached. Did you mean case1 have concern about "posted write", and you want to know why it not matter? case2 will be safer? Case1 : spin_lock_irq_save() writel(0, target register) spin_unlock_irqrestore() Case2 : spin_lock_irq_save() tmp = readl(target register) tmp &= ~(bit4 | bit5) writel(tmp, target register) spin_unlock_irqrestore() I test uart port with linux-serial-test tool. Ex. send char linux-serial-test -y 0x55 -z 0x31 -p /dev/ttySUPx -b 115200 driver will call from uart startup till uart shutdown. And it works fine, so I didn't think about "posted write" on Register bus. > -- > js > suse labs
