Hi All,
I'm really sorry for sending the wrong specified file. Please ignore
the email. I will resend V4.
On 2022/1/10 16:26, Yu Tu wrote:
The UART_REG5 register defaults to 0. The console port is set in
ROMCODE. But other UART ports default to 0, so make bit24 and
bit[26,27] writable so that the UART can choose a more
appropriate clock.
Signed-off-by: Yu Tu <yu.tu@xxxxxxxxxxx>
---
drivers/tty/serial/meson_uart.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/meson_uart.c b/drivers/tty/serial/meson_uart.c
index 7c3f30cea68e..b0551750dff8 100644
--- a/drivers/tty/serial/meson_uart.c
+++ b/drivers/tty/serial/meson_uart.c
@@ -693,7 +693,7 @@ static int meson_uart_probe_clocks(struct uart_port *port)
CLK_SET_RATE_NO_REPARENT,
port->membase + AML_UART_REG5,
26, 2,
- CLK_DIVIDER_READ_ONLY,
+ CLK_DIVIDER_ROUND_CLOSEST,
xtal_div_table, NULL);
if (IS_ERR(hw))
return PTR_ERR(hw);
@@ -719,7 +719,7 @@ static int meson_uart_probe_clocks(struct uart_port *port)
CLK_SET_RATE_PARENT,
port->membase + AML_UART_REG5,
24, 0x1,
- CLK_MUX_READ_ONLY,
+ CLK_MUX_ROUND_CLOSEST,
NULL, NULL);
if (IS_ERR(hw))
return PTR_ERR(hw);
base-commit: 93a770b7e16772530196674ffc79bb13fa927dc6
prerequisite-patch-id: 95191c926509964c8e9bf4128b8bbad8a277b84a
prerequisite-patch-id: a2e4756ff85f0df0efe111d7e2cb51b8e26e226f
prerequisite-patch-id: 4e4d909acabcb7533da20e2207207be73454a88c
