Hi Matthias, On Thu, 2021-12-30 at 14:18 +0100, Matthias Brugger wrote: > > On 28/04/2021 08:54, Roger Lu wrote: > > 1. SVS driver uses OPP adjust event in [1] to update OPP table voltage part. > > 2. SVS driver gets thermal/GPU device by node [2][3] and CPU device by > > get_cpu_device(). > > After retrieving subsys device, SVS driver calls device_link_add() to make > > sure probe/suspend callback priority. > > 3. SVS dts refers to reset controller [4] to help reset SVS HW. > > > > #mt8183 SVS related patches > > [1] > > https://urldefense.com/v3/__https://patchwork.kernel.org/patch/11193513/__;!!CTRNKA9wMg0ARbw!yy2e7JqE__BQAZF3jwBuR3Fbzbv8LPxwwA3l6SVu7SFAG94dCHyVq9A3MIscKXW-$ > > > > Already mainline, please either refer to the commit, to make it clear it's > maineline or drop it. > > > [2] > > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20201013102358.22588-2-michael.kao@xxxxxxxxxxxx/__;!!CTRNKA9wMg0ARbw!yy2e7JqE__BQAZF3jwBuR3Fbzbv8LPxwwA3l6SVu7SFAG94dCHyVq9A3ML35Ale5$ > > > > Same here. > > > [3] > > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20200306041345.259332-3-drinkcat@xxxxxxxxxxxx/__;!!CTRNKA9wMg0ARbw!yy2e7JqE__BQAZF3jwBuR3Fbzbv8LPxwwA3l6SVu7SFAG94dCHyVq9A3MMUMr7Oh$ > > > > Same here, Thanks for the review. I'll refer to mainline or the latest reviewing patch. > > > > > #mt8192 SVS related patches > > [1] > > https://urldefense.com/v3/__https://patchwork.kernel.org/patch/11193513/__;!!CTRNKA9wMg0ARbw!yy2e7JqE__BQAZF3jwBuR3Fbzbv8LPxwwA3l6SVu7SFAG94dCHyVq9A3MIscKXW-$ > > > > Same here, it's actually the same link as [1]. > > > [2] > > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20201223074944.2061-1-michael.kao@xxxxxxxxxxxx/__;!!CTRNKA9wMg0ARbw!yy2e7JqE__BQAZF3jwBuR3Fbzbv8LPxwwA3l6SVu7SFAG94dCHyVq9A3MEUxFEDM$ > > > > [3] > > https://urldefense.com/v3/__https://lore.kernel.org/patchwork/patch/1360551/__;!!CTRNKA9wMg0ARbw!yy2e7JqE__BQAZF3jwBuR3Fbzbv8LPxwwA3l6SVu7SFAG94dCHyVq9A3MNObUeLt$ > > > > [4] > > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20200817030324.5690-5-crystal.guo@xxxxxxxxxxxx/__;!!CTRNKA9wMg0ARbw!yy2e7JqE__BQAZF3jwBuR3Fbzbv8LPxwwA3l6SVu7SFAG94dCHyVq9A3MMx-JKoe$ > > > > There are many dependencies for that. Some patches need resubmit, others seem > to > be stale. I'd advise to concentrate on mt8183 for now and add support for > mt8192 > once dependencies have settled. Sure, let's concentrate on mt8183 patches first. Thanks for sharing the advice. > > Regards, > Matthias > > > > > changes since v15: > > - Put (*set_freqs_pct) and (*get_vops) in struct svs_bank because they are > > part of svs bank's operation > > - Add define "SVSB_INIT02_RM_DVTFIXED" and "SVSB_MON_VOLT_IGNORE" to make > > control clearly. > > - Remove unnecessary parenthesis > > > > Roger Lu (7): > > [v16,1/7] dt-bindings: soc: mediatek: add mtk svs dt-bindings > > [v16,2/7] arm64: dts: mt8183: add svs device information > > [v16,3/7] soc: mediatek: SVS: introduce MTK SVS engine > > [v16,4/7] soc: mediatek: SVS: add debug commands > > [v16,5/7] dt-bindings: soc: mediatek: add mt8192 svs dt-bindings > > [v16,6/7] arm64: dts: mt8192: add svs device information > > [v16,7/7] soc: mediatek: SVS: add mt8192 SVS GPU driver > > > > .../bindings/soc/mediatek/mtk-svs.yaml | 92 + > > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 18 + > > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34 + > > drivers/soc/mediatek/Kconfig | 10 + > > drivers/soc/mediatek/Makefile | 1 + > > drivers/soc/mediatek/mtk-svs.c | 2524 +++++++++++++++++ > > 6 files changed, 2679 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mtk- > > svs.yaml > > create mode 100644 drivers/soc/mediatek/mtk-svs.c > > > > _______________________________________________ > > Linux-mediatek mailing list > > Linux-mediatek@xxxxxxxxxxxxxxxxxxx > > https://urldefense.com/v3/__http://lists.infradead.org/mailman/listinfo/linux-mediatek__;!!CTRNKA9wMg0ARbw!yy2e7JqE__BQAZF3jwBuR3Fbzbv8LPxwwA3l6SVu7SFAG94dCHyVq9A3MIj4Pohu$ > > > >
