This phy can be used as pcie-phy, usb3-phy, sata-phy or sgmii-phy. Changes in v7: - remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel - rename regs Changes in v5: - modify description for ssc and ext-refclk - remove apb reset - add rockchip_combphy_updatel() - restyle Changes in v4: - restyle - remove some minItems - add more properties - remove reset-names - move #phy-cells - add rockchip,rk3568-pipe-grf - add rockchip,rk3568-pipe-phy-grf - add devm_reset_control_array_get() - remove clk structure - change refclk DT parse - change dev_err message - add dot to phrase - add ext_refclk variable - add enable_ssc variable - rename rockchip_combphy_param_write - remove param_read - replace rockchip-naneng-combphy driver name - rename node name Changes in v3: - Using api devm_reset_control_get_optional_exclusive and dev_err_probe. - Remove apb_rst. - Redefine registers address. - Move pipe_phy_grf0 to rk3568.dtsi Changes in v2: - Fix dtschema/dtc warnings/errors - Using api devm_platform_get_and_ioremap_resource. - Modify rockchip_combphy_set_Mode. - Add some PHY registers definition. - Move phy0 to rk3568.dtsi Johan Jonker (1): dt-bindings: mfd: syscon: add naneng combo phy register compatible Yifeng Zhao (3): dt-bindings: phy: rockchip: Add Naneng combo PHY bindings phy: rockchip: add naneng combo phy for RK3568 arm64: dts: rockchip: add naneng combo phy nodes for rk3568 .../devicetree/bindings/mfd/syscon.yaml | 2 + .../phy/phy-rockchip-naneng-combphy.yaml | 109 ++++ arch/arm64/boot/dts/rockchip/rk3568.dtsi | 21 + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 47 ++ drivers/phy/rockchip/Kconfig | 8 + drivers/phy/rockchip/Makefile | 1 + .../rockchip/phy-rockchip-naneng-combphy.c | 589 ++++++++++++++++++ 7 files changed, 777 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c -- 2.17.1
