Hi Birger, On Tue, 2021-12-28 at 17:53 +0100, Birger Koblitz wrote: > On 28/12/2021 17:21, Sander Vanheule wrote: > > On Mon, 2021-12-27 at 11:17 +0000, Marc Zyngier wrote: > > > On Sun, 26 Dec 2021 19:59:27 +0000, > > > Sander Vanheule <sander@xxxxxxxxxxxxx> wrote: > > > > interrupts: > > > > - maxItems: 1 > > > > + minItems: 1 > > > > + maxItems: 15 > > > > + description: > > > > + List of parent interrupts, in the order that they are connected to this > > > > + interrupt router's outputs. > > > > > > Is that to support multiple SoCs? I'd expect a given SoC to have a > > > fixed number of output interrupts. > > > > It is, and they do AFAICT. But all values from 1 to 15 can be written to the routing > > registers, so I wanted this definition to be as broad as possible. > > > > The SoCs I'm working with only connect to the six CPU HW interrupts, but I don't know > > what > > the actual limit of this interrupt hardware is, or if the outputs always connect to > > the > > MIPS CPU HW interrupts. > > > From what I know, the IRQ controller is used solely by Realtek in the RTL838x, RTL839x > and > RTL930x SoC families, all of them MIPS 4KEc or 34Kc with the standard 7 CPU IRQ lines. > In their final RTL931x series they abandoned their custom IRQ controller and went for > an InterAptiv core with a standard MIPS GIC. There is some code floating around [1] to support a few Wi-Fi SoCs (RTL8196E, RTL8197D, and RTL8197F) which appear to use the same interrupt controller. Not that it's very likely these will ever be supported property, because they contain Lexra MIPS cores. That code claims these cores can have 16 CPU interrupts, althought the non-standard interrupts are apparently not implemented in that driver. There is also mention of 64 SoC interrupts, but it looks like this can be implemented by just instantiating this driver once for each register range (given the code would be modified to get rid of some static variables). Anyway, a mostly theoretical problem. The SoCs we're targetting (RTL8380x, RTL839x, and RTL930x) use the /6/ MIPS CPU HW interrupts (the two software interrupts are not used AFAICT). [1] https://github.com/ggbruno/openwrt/blob/Realtek/target/linux/realtek/files-4.14/arch/mips/realtek/irq.c Best, Sander
