From: Yifeng Zhao <yifeng.zhao@xxxxxxxxxxxxxx>
Add the core DT nodes for the rk3568 Naneng multi phys.
Signed-off-by: Yifeng Zhao <yifeng.zhao@xxxxxxxxxxxxxx>
Signed-off-by: Johan Jonker <jbx6244@xxxxxxxxx>
---
arch/arm64/boot/dts/rockchip/rk3566.dtsi | 4 ++
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 23 +++++++++++
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 50 ++++++++++++++++++++++++
3 files changed, 77 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3566.dtsi b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
index 3839eef5e..af442e83b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
@@ -6,6 +6,10 @@
compatible = "rockchip,rk3566";
};
+&multiphy {
+ compatible = "rockchip,rk3566-naneng-multiphy";
+};
+
&power {
power-domain@RK3568_PD_PIPE {
reg = <RK3568_PD_PIPE>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index 2fd313a29..22bc0e85b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -8,6 +8,11 @@
/ {
compatible = "rockchip,rk3568";
+ pipe_phy_grf0: syscon@fdc70000 {
+ compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
+ reg = <0x0 0xfdc70000 0x0 0x1000>;
+ };
+
qos_pcie3x1: qos@fe190080 {
compatible = "rockchip,rk3568-qos", "syscon";
reg = <0x0 0xfe190080 0x0 0x20>;
@@ -80,6 +85,24 @@
};
};
+&multiphy {
+ compatible = "rockchip,rk3568-naneng-multiphy";
+
+ multiphy0: multi-phy@fe820000 {
+ reg = <0x0 0xfe820000 0x0 0x100>;
+ clocks = <&pmucru CLK_PCIEPHY0_REF>,
+ <&cru PCLK_PIPEPHY0>,
+ <&cru PCLK_PIPE>;
+ clock-names = "ref", "apb", "pipe";
+ assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
+ assigned-clock-rates = <100000000>;
+ resets = <&cru SRST_PIPEPHY0>;
+ rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+};
+
&power {
power-domain@RK3568_PD_PIPE {
reg = <RK3568_PD_PIPE>;
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 46d9552f6..32e5c8026 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -214,11 +214,26 @@
};
};
+ pipegrf: syscon@fdc50000 {
+ compatible = "rockchip,rk3568-pipe-grf", "syscon";
+ reg = <0x0 0xfdc50000 0x0 0x1000>;
+ };
+
grf: syscon@fdc60000 {
compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
reg = <0x0 0xfdc60000 0x0 0x10000>;
};
+ pipe_phy_grf1: syscon@fdc80000 {
+ compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
+ reg = <0x0 0xfdc80000 0x0 0x1000>;
+ };
+
+ pipe_phy_grf2: syscon@fdc90000 {
+ compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
+ reg = <0x0 0xfdc90000 0x0 0x1000>;
+ };
+
pmucru: clock-controller@fdd00000 {
compatible = "rockchip,rk3568-pmucru";
reg = <0x0 0xfdd00000 0x0 0x1000>;
@@ -1077,6 +1092,41 @@
status = "disabled";
};
+ multiphy: multiphy {
+ rockchip,pipe-grf = <&pipegrf>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ status = "disabled";
+
+ multiphy1: multi-phy@fe830000 {
+ reg = <0x0 0xfe830000 0x0 0x100>;
+ clocks = <&pmucru CLK_PCIEPHY1_REF>,
+ <&cru PCLK_PIPEPHY1>,
+ <&cru PCLK_PIPE>;
+ clock-names = "ref", "apb", "pipe";
+ assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
+ assigned-clock-rates = <100000000>;
+ resets = <&cru SRST_PIPEPHY1>;
+ rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
+ multiphy2: multi-phy@fe840000 {
+ reg = <0x0 0xfe840000 0x0 0x100>;
+ clocks = <&pmucru CLK_PCIEPHY2_REF>,
+ <&cru PCLK_PIPEPHY2>,
+ <&cru PCLK_PIPE>;
+ clock-names = "ref", "apb", "pipe";
+ assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
+ assigned-clock-rates = <100000000>;
+ resets = <&cru SRST_PIPEPHY2>;
+ rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+ };
+
pinctrl: pinctrl {
compatible = "rockchip,rk3568-pinctrl";
rockchip,grf = <&grf>;
--
2.20.1
