On Tue, 21 Dec 2021 09:47:09 +0000, Lad Prabhakar wrote:
> From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
>
> Define RZ/V2L (R9A07G054) Clock Pulse Generator Core Clock and module
> clock outputs, as listed in Table 7.1.4.2 ("Clock List r1.0") and also
> add Reset definitions referring to registers CPG_RST_* in Section 7.2.3
> ("Register configuration") of the RZ/V2L Hardware User's Manual (Rev.1.00,
> Nov.2021).
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> ---
> include/dt-bindings/clock/r9a07g054-cpg.h | 226 ++++++++++++++++++++++
> 1 file changed, 226 insertions(+)
> create mode 100644 include/dt-bindings/clock/r9a07g054-cpg.h
>
Acked-by: Rob Herring <robh@xxxxxxxxxx>
