Re: [PATCH v5 2/2] serial:sunplus-uart:Add Sunplus SoC UART Driver

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On Mon, Dec 13, 2021 at 03:10:07PM +0800, Hammer Hsieh wrote:
> +/* Register offsets */
> +#define SUP_UART_DATA			0x00
> +#define SUP_UART_LSR			0x04
> +#define SUP_UART_MSR			0x08
> +#define SUP_UART_LCR			0x0C
> +#define SUP_UART_MCR			0x10
> +#define SUP_UART_DIV_L			0x14
> +#define SUP_UART_DIV_H			0x18
> +#define SUP_UART_ISC			0x1C
> +#define SUP_UART_TX_RESIDUE		0x20
> +#define SUP_UART_RX_RESIDUE		0x24
> +
> +/* Line Status Register bits */
> +#define SUP_UART_LSR_TXE		BIT(6) /* tx empty */
> +#define SUP_UART_LSR_BC			BIT(5) /* break condition status */
> +#define SUP_UART_LSR_FE			BIT(4) /* frame error status */
> +#define SUP_UART_LSR_OE			BIT(3) /* overrun error status */
> +#define SUP_UART_LSR_PE			BIT(2) /* parity error status */
> +#define SUP_UART_LSR_RX			BIT(1) /* 1: receive fifo not empty */
> +#define SUP_UART_LSR_TX			BIT(0) /* 1: transmit fifo is not full */
> +#define SUP_UART_LSR_TX_NOT_FULL	1
> +#define SUP_UART_LSR_BRK_ERROR_BITS	GENMASK(5, 2)
> +
> +/* Line Control Register bits */
> +#define SUP_UART_LCR_BC			BIT(5) /* break condition select */
> +#define SUP_UART_LCR_PR			BIT(4) /* parity bit polarity select */
> +#define SUP_UART_LCR_PE			BIT(3) /* parity bit enable */
> +#define SUP_UART_LCR_ST			BIT(2) /* stop bits select */
> +#define SUP_UART_LCR_WL5		0x00 /*  word length 5 */
> +#define SUP_UART_LCR_WL6		0x01 /*  word length 6 */
> +#define SUP_UART_LCR_WL7		0x02 /*  word length 7 */
> +#define SUP_UART_LCR_WL8		0x03 /*  word length 8 (default) */
> +
> +/* Modem Control Register bits */
> +#define SUP_UART_MCR_LB			BIT(4) /* Loopback mode */
> +#define SUP_UART_MCR_RI			BIT(3) /* ring indicator */
> +#define SUP_UART_MCR_DCD		BIT(2) /* data carrier detect */
> +#define SUP_UART_MCR_RTS		BIT(1) /* request to send */
> +#define SUP_UART_MCR_DTS		BIT(0) /* data terminal ready */
> +
> +/* Interrupt Status/Control Register bits */
> +#define SUP_UART_ISC_RXM		BIT(5) /* RX interrupt enable */
> +#define SUP_UART_ISC_TXM		BIT(4) /* TX interrupt enable */
> +#define SUP_UART_ISC_RX			BIT(1) /* RX interrupt status */
> +#define SUP_UART_ISC_TX			BIT(0) /* TX interrupt status */
> +
> +#define SUP_DUMMY_READ			BIT(16) /* drop bytes received on a !CREAD port */
> +#define SUP_UART_NR			5

Aren't most of these defines already in the kernel header files?  Why
create them again?




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