Introduce "intel,socfpga-qspi" as the compatible for the Cadence QSPI controller that is on all flavors of SoCFPGA devices: Cyclone5/Arria5/Arria10/Stratix10/Agilex/N5X The reason for this change is because the standard driver recently introduced a patch to write to the CQSPI_REG_WR_COMPLETION_CTRL without any condition. But the QSPI controller that is on the SoCFPGA platforms does not implement the CQSPI_REG_WR_COMPLETION_CTRL register, thus a write to this register, results in a kernel crash. I don't believe we need a chip specific compatible for each chip because the MODULE_ID for all flavors of SoCFPGA is identical. Thus, I think the "intel,socfpga-qspi" compatible is appropriate to cover all variants of the SoCFPGA platform. Dinh Nguyen (2): dt-bindings: spi: cadence-quadspi: document "intel,socfpga-qspi" ARM: dts: socfpga: change qspi to "intel,socfpga-qspi" Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml | 1 + arch/arm/boot/dts/socfpga.dtsi | 2 +- arch/arm/boot/dts/socfpga_arria10.dtsi | 2 +- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 2 +- arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 +- 5 files changed, 5 insertions(+), 4 deletions(-) -- 2.25.1
