On Wed, Dec 15, 2021 at 06:36:08PM +0800, Dejia Shang wrote: > To enable this NPU IP in Arm-Linux system, SoC vendors should > write devicetree files as documented. > > Signed-off-by: Dejia Shang <dejia.shang@xxxxxxxxxxxx> > --- > .../bindings/misc/armchina,zhouyi-npu.yaml | 57 +++++++++++++++++++ > .../devicetree/bindings/vendor-prefixes.yaml | 2 + > 2 files changed, 59 insertions(+) > create mode 100644 Documentation/devicetree/bindings/misc/armchina,zhouyi-npu.yaml > > diff --git a/Documentation/devicetree/bindings/misc/armchina,zhouyi-npu.yaml b/Documentation/devicetree/bindings/misc/armchina,zhouyi-npu.yaml > new file mode 100644 > index 000000000000..d3fdea101114 > --- /dev/null > +++ b/Documentation/devicetree/bindings/misc/armchina,zhouyi-npu.yaml > @@ -0,0 +1,57 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/misc/armchina,zhouyi-npu.yaml#"; > +$schema: "http://devicetree.org/meta-schemas/core.yaml#"; > + > +title: ArmChina Zhouyi NPU bindings > + > +maintainers: > + - Dejia Shang <dejia.shang@xxxxxxxxxxxx> > + > +description: | > + Armchina AI accelerator IP - Zhouyi NPU > + > +properties: > + compatible: > + items: > + - const: armchina,zhouyi-v1 > + - const: armchina,zhouyi-v2 > + - const: armchina,zhouyi This says compatible must be a list of all 3 of these. Where do v1 and v2 come from? We don't do version numbers in DT usually unless they correspond to h/w revision registers or h/w documentation. I would assume the h/w follows the Arm rXpY form? > + > + reg: > + maxItems: 1 > + > + memory-region: > + maxItems: 2 What is each region? This requires 2 entries, but the example only has 1. > + > + interrupts: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - interrupts > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + aipu_ddr_reserved: aipu-shmem@0xA0000000 { aipu-shmem@a0000000 > + compatible = "shared-dma-pool"; > + no-map; > + reg = <0x0 0xA0000000 0x0 0x4000000>; > + }; > + }; > + > + aipu0@0x64000000 { Drop '0x' > + compatible = "armchina,zhouyi"; > + reg = <0x0 0x64000000 0x0 0x1000>; > + memory-region=<&aipu_ddr_reserved>; > + interrupts = <0 168 1>; > + }; > diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml > index 66d6432fd781..4b1865d92455 100644 > --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml > +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml > @@ -123,6 +123,8 @@ patternProperties: > description: ARM Ltd. > "^armadeus,.*": > description: ARMadeus Systems SARL > + "^armchina,.*": > + description: Arm Technology (China) Co., Ltd. > "^arrow,.*": > description: Arrow Electronics > "^artesyn,.*": > -- > 2.17.1 > > IMPORTANT NOTICE: The contents of this email and any attachments may be privileged and confidential. If you are not the intended recipient, please delete the email immediately. It is strictly prohibited to disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ©Arm Technology (China) Co., Ltd copyright and reserve all rights. 重要提示：本邮件（包括任何附件）可能含有专供明确的个人或目的使用的机密信息，并受法律保护。如果您并非该收件人，请立即删除此邮件。严禁通过任何渠道，以任何目的，向任何人披露、储存或复制邮件信息或者据此采取任何行动。感谢您的配合。 ©安谋科技（中国）有限公司 版权所有并保留一切权利。 >
