Quoting Emil Renner Berthing (2021-11-16 07:01:08) > From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> > > Add bindings for the clock generator on the JH7100 RISC-V SoC by > StarFive Ltd. This is a test chip for their upcoming JH7110 SoC. > > Signed-off-by: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> > Signed-off-by: Emil Renner Berthing <kernel@xxxxxxxx> > Reviewed-by: Rob Herring <robh@xxxxxxxxxx> > --- Acked-by: Stephen Boyd <sboyd@xxxxxxxxxx>
