On Mon, Nov 29, 2021 at 10:53:37PM +0000, Robin Murphy wrote:
> On 2021-11-29 21:06, Rob Herring wrote:
> > On Fri, Nov 12, 2021 at 02:19:04PM +0100, Thierry Reding wrote:
> > > From: Thierry Reding <treding@xxxxxxxxxx>
> > >
> > > The NVIDIA Tegra234 SoC has 3 clusters of 4 Cortex-A78AE CPU cores each,
> > > for a total of 12 CPUs. Each CPU has 64 KiB instruction and data caches
> > > with each cluster having an additional 256 KiB unified L2 cache and a 2
> > > MiB L3 cache.
> > >
> > > Signed-off-by: Thierry Reding <treding@xxxxxxxxxx>
> > > ---
> > > arch/arm64/boot/dts/nvidia/tegra234.dtsi | 365 ++++++++++++++++++++++-
> > > 1 file changed, 363 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> > > index 104e5fdd5f8a..db24f48edc9f 100644
> > > --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> > > +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> > > @@ -736,12 +736,373 @@ cpus {
> > > #address-cells = <1>;
> > > #size-cells = <0>;
> > > - cpu@0 {
> > > + cpu0_0: cpu@0 {
> > > + compatible = "arm,cortex-a78";
> > > device_type = "cpu";
> > > - reg = <0x000>;
> > > + reg = <0x00000>;
> > > enable-method = "psci";
> > > +
> >
> > > + i-cache-size = <65536>;
> > > + i-cache-line-size = <64>;
> > > + i-cache-sets = <256>;
> > > + d-cache-size = <65536>;
> > > + d-cache-line-size = <64>;
> > > + d-cache-sets = <256>;
> >
> > Isn't all this discoverable?
>
> No. The required parameters for cache maintenance by set/way are
> discoverable from the CTR, and if you're particularly lucky they might even
> happen to reflect the underlying physical cache structures, but there's
> absolutely no guarantee of that, and there definitely exist cases where they
> don't.
>
> [...]
> > > + pmu {
> > > + compatible = "arm,armv8-pmuv3";
>
> Oh, I'd missed this - per the current state of things, we should really have
> a proper compatible for the PMU as well.
Good catch! I've changed this to arm,cortex-a78-pmu since that's what
Tegra234 has.
Thanks,
Thierry
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