On Wed, Dec 08, 2021 at 08:14:33PM +0300, Dmitry Baryshkov wrote: > Document the PCIe DT bindings for SM8450 SoC.The PCIe IP is similar > to the one used on SM8250. Add the compatible for SM8450. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> Note to self: This binding should be converted to YAML very soon. Thanks, Mani > --- > .../devicetree/bindings/pci/qcom,pcie.txt | 21 ++++++++++++++++++- > 1 file changed, 20 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt > index a0ae024c2d0c..73bc763c5009 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt > @@ -15,6 +15,7 @@ > - "qcom,pcie-sc8180x" for sc8180x > - "qcom,pcie-sdm845" for sdm845 > - "qcom,pcie-sm8250" for sm8250 > + - "qcom,pcie-sm8450" for sm8450 > - "qcom,pcie-ipq6018" for ipq6018 > > - reg: > @@ -169,6 +170,24 @@ > - "ddrss_sf_tbu" PCIe SF TBU clock > - "pipe" PIPE clock > > +- clock-names: > + Usage: required for sm8450 > + Value type: <stringlist> > + Definition: Should contain the following entries > + - "aux" Auxiliary clock > + - "cfg" Configuration clock > + - "bus_master" Master AXI clock > + - "bus_slave" Slave AXI clock > + - "slave_q2a" Slave Q2A clock > + - "tbu" PCIe TBU clock > + - "ddrss_sf_tbu" PCIe SF TBU clock > + - "pipe" PIPE clock > + - "pipe_mux" PIPE MUX > + - "phy_pipe" PIPE output clock > + - "ref" REFERENCE clock > + - "aggre0" Aggre NoC PCIe0 AXI clock > + - "aggre1" Aggre NoC PCIe1 AXI clock > + > - resets: > Usage: required > Value type: <prop-encoded-array> > @@ -246,7 +265,7 @@ > - "ahb" AHB reset > > - reset-names: > - Usage: required for sc8180x, sdm845 and sm8250 > + Usage: required for sc8180x, sdm845, sm8250 and sm8450 > Value type: <stringlist> > Definition: Should contain the following entries > - "pci" PCIe core reset > -- > 2.33.0 >
