On Sat, Dec 04, 2021 at 11:58:15PM +0200, Sam Protsenko wrote: > In new Exynos SoCs (like Exynos850) where HSI2C is implemented as a > part of USIv2 block, there are two clocks provided to HSI2C controller: > - PCLK: bus clock (APB), provides access to register interface > - IPCLK: operating IP-core clock; SCL is derived from this one > > Both clocks have to be asserted for HSI2C to be functional in that case. > > Modify bindings doc to allow specifying bus clock in addition to > already described operating clock. > > Signed-off-by: Sam Protsenko <semen.protsenko@xxxxxxxxxx> Applied to for-next, thanks!
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