On Tue, Dec 07, 2021 at 06:20:42PM +0000, Robin Murphy wrote:
> Convert the DSU binding to schema, as one does.
>
> Signed-off-by: Robin Murphy <robin.murphy@xxxxxxx>
> ---
> .../devicetree/bindings/arm/arm-dsu-pmu.txt | 27 ------------
> .../devicetree/bindings/perf/arm,dsu-pmu.yaml | 41 +++++++++++++++++++
> 2 files changed, 41 insertions(+), 27 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
> create mode 100644 Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt b/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
> deleted file mode 100644
> index 6efabba530f1..000000000000
> --- a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
> +++ /dev/null
> @@ -1,27 +0,0 @@
> -* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
> -
> -ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores
> -with a shared L3 memory system, control logic and external interfaces to
> -form a multicore cluster. The PMU enables to gather various statistics on
> -the operations of the DSU. The PMU provides independent 32bit counters that
> -can count any of the supported events, along with a 64bit cycle counter.
> -The PMU is accessed via CPU system registers and has no MMIO component.
> -
> -** DSU PMU required properties:
> -
> -- compatible : should be one of :
> -
> - "arm,dsu-pmu"
> -
> -- interrupts : Exactly 1 SPI must be listed.
> -
> -- cpus : List of phandles for the CPUs connected to this DSU instance.
> -
> -
> -** Example:
> -
> -dsu-pmu-0 {
> - compatible = "arm,dsu-pmu";
> - interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>;
> - cpus = <&cpu_0>, <&cpu_1>;
> -};
> diff --git a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
> new file mode 100644
> index 000000000000..b78b6b0fce66
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
> @@ -0,0 +1,41 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright 2021 Arm Ltd.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/perf/arm,dsu-pmu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
> +
> +maintainers:
> + - Suzuki K Poulose <suzuki.poulose@xxxxxxx>
> + - Robin Murphy <robin.murphy@xxxxxxx>
> +
> +description:
> + ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores with a shared
> + L3 memory system, control logic and external interfaces to form a multicore
> + cluster. The PMU enables gathering various statistics on the operation of the
> + DSU. The PMU provides independent 32-bit counters that can count any of the
> + supported events, along with a 64-bit cycle counter. The PMU is accessed via
> + CPU system registers and has no MMIO component.
> +
> +properties:
> + compatible:
> + const: "arm,dsu-pmu"
Don't need quotes.
> +
> + interrupts:
> + items:
> + description: nCLUSTERPMUIRQ interrupt
- description: nCLUSTERPMUIRQ interrupt
> +
> + cpus:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + minitems: 1
> + maxitems: 8
> + description: List of phandles for the CPUs connected to this DSU instance.
> +
> +required:
> + - compatible
> + - interrupts
> + - cpus
> +
> +additionalProperties: false
> --
> 2.28.0.dirty
>
>
