On Mon, 6 Dec 2021 at 17:32, David Virag <virag.david003@xxxxxxxxx> wrote:
>
> pll1417x is used in Exynos7885 SoC for top-level integer PLLs.
> It is similar enough to pll0822x that practically the same code can
> handle both. The difference that's to be noted is that when defining a
> pl1417x PLL, the "con" parameter of the PLL macro should be set to the
> CON1 register instead of CON3, like this:
>
> PLL(pll_1417x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
> PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0,
> NULL),
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxxxxx>
> Signed-off-by: David Virag <virag.david003@xxxxxxxxx>
> ---
> Changes in v2:
> - Nothing
>
> Changes in v3:
> - Nothing
>
> Changes in v4:
> - Added R-b tag by Krzysztof Kozlowski
>
> drivers/clk/samsung/clk-pll.c | 1 +
> drivers/clk/samsung/clk-pll.h | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
> index 83d1b03647db..70cdc87f714e 100644
> --- a/drivers/clk/samsung/clk-pll.c
> +++ b/drivers/clk/samsung/clk-pll.c
> @@ -1476,6 +1476,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
> else
> init.ops = &samsung_pll35xx_clk_ops;
> break;
> + case pll_1417x:
I wonder why this switch have a bunch of fall through cases, but none
marked with "fallthrough;" line, and both checkpatch and "make" turn
blind eye on that? Anyway, I guess it's ok as is, just an observation.
Reviewed-by: Sam Protsenko <semen.protsenko@xxxxxxxxxx>
> case pll_0822x:
> pll->enable_offs = PLL0822X_ENABLE_SHIFT;
> pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT;
> diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
> index a739f2b7ae80..c83a20195f6d 100644
> --- a/drivers/clk/samsung/clk-pll.h
> +++ b/drivers/clk/samsung/clk-pll.h
> @@ -32,6 +32,7 @@ enum samsung_pll_type {
> pll_2550xx,
> pll_2650x,
> pll_2650xx,
> + pll_1417x,
> pll_1450x,
> pll_1451x,
> pll_1452x,
> --
> 2.34.1
>
